This is a sub-page of Golden Axe (TurboGrafx-CD).
A massive amount of source code is found throughout track 02.
Chunk 1#
;
include biosw.h
include inf.h
;
player_s equ $3f00
stage_s equ $3f01
mode equ $3ffe
;
seg cseg
entry:
; reno wait !!!
; ldx #$60
;_wait_lp:
; jsr ex_vsync
; dex
; bne _wait_lp
;
; initialize common work !!!
;
clx
_clr_lp:
stz $2000,x
inx
bne _clr_lp
;ゲームのｽﾃｲﾀｽ
PLAYER EQU 2000H ;PLAYATR 退避
STAGE EQU 2001H ;ステージ
PLAY_LAST EQU 2002H ;残奇数
PLAYTUBO EQU 2003H ;魔法レベル
PLAYSCORE EQU 2004H ;得点
PLAYHP EQU 2005H ;体力
CONTINUE EQU 2006H ;ｺﾝﾃｨﾆｭｰ回数
lda #$ff
sta player
sta stage
lda #3
sta play_last
lda #1
sta playtubo
stz playscore
lda #15
sta playhp
lda #3
sta continue
stz mode
lda #visual_bin_hi
sta _cl
lda #high(visual_bin_lw)
sta _ch
lda #low(visual_bin_lw)
sta _dl
lda #01
sta _dh
lda #low($4000)
sta _bl
lda #high($4000)
sta _bh
lda #visual_bin_rl
sta _al
sei
jsr cd_exec
;
endChunk 2#
;
; DEATH ADDER (Middle)
;
include macro.h
include visual.h
include biosw.h
include c62.h
include uty.h
include inf_e.h
;
stage equ $3f00
player equ $3f01
mode equ $3ffe
;
public entry
;
seg dseg
pal_work ds 4096
seg cseg
entry:
jmp startup
ifdef tyris
data1:
; data C1_PCB,pal_work,1,LOCAL
; data T1B_CCB,pal_work+512,1,LOCAL
; data T2_CCB,pal_work+512*2,1,LOCAL
; data T2B_CCB,pal_work+512*3,1,LOCAL
; data C1_PBB,$6000,4*2,VRAM
; data T1B_CSB,$5000,4*1,VRAM
; ;mapreg 4,$3a
; ;mapreg 5,$3b
; ;mapreg 6,$3c
; data T2_CBB,$8000,4*1,LOCAL
; data T2A_CAB,$a000,4*1,LOCAL
; data T2B_CSB,$1000,4*1,VRAM
; data T2C_CSB,$2000,4*1,VRAM
; data T2D_CSB,$3000,4*1,VRAM
; data T2E_CSB,$4000,4*1,VRAM
; data T2F_CSB,$c000,4*1,LOCAL
data tc001_,pal_work,2,LOCAL
data tv001_,$8000,4*1,LOCAL
data ta001_,$a000,4*1,LOCAL
data tv001b_,$1000,4*7,VRAM
data tv001c_,$c000,4*1,LOCAL
enddata
data2:
; data T3_CCB,pal_work,1,LOCAL
; data T3B_CCB,pal_work+512,1,LOCAL
; ;mapreg 4,$3a
; ;mapreg 5,$3b
; ;mapreg 6,$3c
; data T3A_CAB,$8000,4*1,LOCAL
; data T3_CBB,$a000,4*1,LOCAL
; data T3B_CSB,$c000,4*1,LOCAL
data tc003_,pal_work,2,LOCAL
data ta003_,$8000,4*1,LOCAL
data tv003_,$a000,4*2,LOCAL
enddata
data3:
; data T4_CCB,pal_work+512*2,1,LOCAL
; data T4B_CCB,pal_work+512*3,1,LOCAL
; data T4_CBB,$7000,4*1,VRAM
; ;mapreg 4,$3d
; ;mapreg 5,$3e
; ;mapreg 6,$3f
; data T4A_CAB,$8000,4*1,LOCAL
; data T4B_CSB,$a000,4*1,LOCAL
; data T4C_CSB,$c000,4*1,LOCAL
data tv004_,$7000,4*1,VRAM
data ta004_,$8000,4*1,LOCAL
data tv004b_,$a000,4*2,LOCAL
enddata
data4:
; data C5A_CCB,pal_work+512*4,1,LOCAL
; data C5B_CCB,pal_work+512*5,1,LOCAL
; data T5_CCB,pal_work+512*5+$20,1,LOCAL
; data C6_CCB,pal_work+512*6,1,LOCAL
; data C6B_CCB,pal_work+512*7,1,LOCAL
; data C5A_CBB,$0000,4*1,ADPCM
; data C5B_CSB,$2000,4*1,ADPCM
; data C5C_CSB,$4000,4*1,ADPCM
; data C5D_CSB,$6000,4*1,ADPCM
; data T5_CSB,$8000,4*1,ADPCM
; data C6_CBB,$a000,4*1,ADPCM
; data C6B_CSB,$c000,4*1,ADPCM
; data C6C_CSB,$e000,4*1,ADPCM
data tv005_,$0000,4*8,ADPCM
enddata
data5:
; ;mapreg 4,$3a
; ;mapreg 5,$3b
; ;mapreg 6,$3c
; data C5AA_CAB,$8000,4*1,LOCAL
; data C6A_CAB,$a000,4*1,LOCAL
; data T7A_CAB,$c000,4*1,LOCAL
data ta005_,$8000,4*1,LOCAL
data ta006_,$a000,4*1,LOCAL
data ta007_,$c000,4*1,LOCAL
enddata
data6:
; ;mapreg 4,$3a
; ;mapreg 5,$3b
; ;mapreg 6,$3c
; data C8_CCB,pal_work,1,LOCAL
; data C8C_CCB,pal_work+512,1,LOCAL
; data C8_CBB,$8000,4*1,LOCAL
; data C8A_CAB,$a000,4*1,LOCAL
; data C8B_CAB,$c000,4*1,LOCAL
; data C8C_CSB,$0000,4*1,ADPCM
; data C8D_CSB,$2000,4*1,ADPCM
; data C8E_CSB,$4000,4*1,ADPCM
; data C8F_CSB,$6000,4*1,ADPCM
; data C8G_CSB,$8000,4*1,ADPCM
data tc008_,pal_work,2,LOCAL
data tv008_,$8000,4*1,LOCAL
data ta008_,$a000,4*1,LOCAL
data ta008b_,$c000,4*1,LOCAL
data tv008b_,$0000,4*5,ADPCM
enddata
data7:
; data T9_CCB,pal_work+512*2,1,LOCAL
; data T9B_CCB,pal_work+512*3,1,LOCAL
; ;mapreg 4,$3d
; ;mapreg 5,$3e
; ;mapreg 6,$3f
; data T9_CBB,$8000,4*1,LOCAL
; data T9A_CAB,$a000,4*1,LOCAL
; data T9B_CSB,$a000,4*1,ADPCM
; data T9C_CSB,$c000,4*1,ADPCM
data tv009_,$8000,4*1,LOCAL
data ta009_,$a000,4*1,LOCAL
data tv009b_,$a000,4*2,ADPCM
enddata
data8:
; data C10A_CCB,pal_work,1,LOCAL
; data C10B_CCB,pal_work+512,1,LOCAL
; data C10A_CBB,$5000,4*1,VRAM
; data C10_CBB,$6000,4*1,VRAM
; ;mapreg 4,$3a
; ;mapreg 5,$3b
; ;mapreg 6,$3c
; data C10A_CAB,$8000,4*1,LOCAL
; data C10B_CSB,$a000,4*1,LOCAL
; data C10C_CSB,$c000,4*1,LOCAL
data tc010_,pal_work,2,LOCAL
data tv010_,$4000,4*3,VRAM
data ta010_,$8000,4*1,LOCAL
data tv010b_,$a000,4*2,LOCAL
enddata
data9:
; data C11_CCB,pal_work+512*2,1,LOCAL
; data T12B_CCB,pal_work+512*3,1,LOCAL
; data C11_CBB,$4000,4*1,VRAM
; ;mapreg 4,$3d
; ;mapreg 5,$3e
; ;mapreg 6,$3f
; data T12A_CAB,$8000,4*1,LOCAL
; data T12B_CSB,$a000,4*1,LOCAL
; data T12C_CSB,$c000,4*1,LOCAL
; data C13_PCB,pal_work,1,LOCAL
; data C13A_CCB,pal_work+512,1,LOCAL
; data C13_PBB,$4000,4*4,VRAM
; ;mapreg 4,$3a
; data C13A_CSB,$8000,4*1,LOCAL
data ta012_,$8000,4*1,LOCAL
data tv012_,$a000,4*2,LOCAL
data tc013_,pal_work+512*4,1,LOCAL
data tv013_,$0000,4*4,ADPCM
data tv013b_,$8000,4*1,ADPCM
enddata
data10:
; data C14_PCB,pal_work+512*2,1,LOCAL
; data T14A_CCB,pal_work+512*3,1,LOCAL
; data C14_PBB,$0000,4*4,ADPCM
; ;mapreg 5,$3b
; data T14A_CSB,$a000,4*1,LOCAL
data tv014_,$0000,4*4,ADPCM
data tv014b_,$a000,4*1,LOCAL
enddata
endif
ifdef battler
data1:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data bc001_,pal_work,2,LOCAL
data bv001_,$8000,4*1,LOCAL
data ba001_,$a000,4*1,LOCAL
data bv001b_,$1000,4*7,VRAM
data bv001c_,$c000,4*1,LOCAL
enddata
data2:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data bc003_,pal_work,2,LOCAL
data ba003_,$8000,4*1,LOCAL
data bv003_,$a000,4*2,LOCAL
enddata
data3:
;mapreg 4,$3d
;mapreg 5,$3e
;mapreg 6,$3f
data bv004_,$7000,4*1,VRAM
data ba004_,$8000,4*1,LOCAL
data bv004b_,$a000,4*2,LOCAL
enddata
data4:
data bv005_,$0000,4*8,ADPCM
enddata
data5:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data ba005_,$8000,4*1,LOCAL
data ba006_,$a000,4*1,LOCAL
data ba007_,$c000,4*1,LOCAL
enddata
data6:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data bc008_,pal_work,2,LOCAL
data bv008_,$8000,4*1,LOCAL
data ba008_,$a000,4*1,LOCAL
data ba008b_,$c000,4*1,LOCAL
data bv008b_,$0000,4*5,ADPCM
enddata
data7:
;mapreg 4,$3d
;mapreg 5,$3e
;mapreg 6,$3f
data bv009_,$8000,4*1,LOCAL
data ba009_,$a000,4*1,LOCAL
data bv009b_,$a000,4*2,ADPCM
enddata
data8:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data bc010_,pal_work,2,LOCAL
data bv010_,$4000,4*3,VRAM
data ba010_,$8000,4*1,LOCAL
data bv010b_,$a000,4*2,LOCAL
enddata
data9:
;mapreg 4,$3d
;mapreg 5,$3e
;mapreg 6,$3f
data ba012_,$8000,4*1,LOCAL
data bv012_,$a000,4*2,LOCAL
data bc013_,pal_work+512*4,1,LOCAL
data bv013_,$0000,4*4,ADPCM
data bv013b_,$8000,4*1,ADPCM
enddata
data10:
;mapreg 4,$3a
;mapreg 5,$3b
data bv014_,$0000,4*4,ADPCM
data bv014b_,$a000,4*1,LOCAL
enddata
endif
ifdef thunder
data1:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data gc001_,pal_work,2,LOCAL
data gv001_,$8000,4*1,LOCAL
data ga001_,$a000,4*1,LOCAL
data gv001b_,$1000,4*7,VRAM
data gv001c_,$c000,4*1,LOCAL
enddata
data2:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data gc003_,pal_work,2,LOCAL
data ga003_,$8000,4*1,LOCAL
data gv003_,$a000,4*2,LOCAL
enddata
data3:
;mapreg 4,$3d
;mapreg 5,$3e
;mapreg 6,$3f
data gv004_,$7000,4*1,VRAM
data ga004_,$8000,4*1,LOCAL
data gv004b_,$a000,4*2,LOCAL
enddata
data4:
data gv005_,$0000,4*8,ADPCM
enddata
data5:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data ga005_,$8000,4*1,LOCAL
data ga006_,$a000,4*1,LOCAL
data ga007_,$c000,4*1,LOCAL
enddata
data6:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data gc008_,pal_work,2,LOCAL
data gv008_,$8000,4*1,LOCAL
data ga008_,$a000,4*1,LOCAL
data ga008b_,$c000,4*1,LOCAL
data gv008b_,$0000,4*5,ADPCM
enddata
data7:
;mapreg 4,$3d
;mapreg 5,$3e
;mapreg 6,$3f
data gv009_,$8000,4*1,LOCAL
data ga009_,$a000,4*1,LOCAL
data gv009b_,$a000,4*2,ADPCM
enddata
data8:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data gc010_,pal_work,2,LOCAL
data gv010_,$4000,4*3,VRAM
data ga010_,$8000,4*1,LOCAL
data gv010b_,$a000,4*2,LOCAL
enddata
data9:
;mapreg 4,$3d
;mapreg 5,$3e
;mapreg 6,$3f
data ga012_,$8000,4*1,LOCAL
data gv012_,$a000,4*2,LOCAL
data gc013_,pal_work+512*4,1,LOCAL
data gv013_,$0000,4*4,ADPCM
data gv013b_,$8000,4*1,ADPCM
enddata
data10:
;mapreg 4,$3a
;mapreg 5,$3b
data gv014_,$0000,4*4,ADPCM
data gv014b_,$a000,4*1,LOCAL
enddata
endif
ifdef audio
audio1:
ifdef tyris
audio mt01_,NORMAL ;0
audio mt02_,NORMAL ;1
audio mt03_,NORMAL ;2
audio mt04_,NORMAL ;3
audio mt05_,NORMAL ;4
audio mt06_,NORMAL ;5
endif
ifdef battler
audio mb01_,NORMAL ;0
audio mb02_,NORMAL ;1
audio mb03_,NORMAL ;2
audio mb04_,NORMAL ;3
audio mb05_,NORMAL ;4
audio mb06_,NORMAL ;5
endif
ifdef thunder
audio mg01_,NORMAL ;0
audio mg02_,NORMAL ;1
audio mg03_,NORMAL ;2
audio mg04_,NORMAL ;3
audio mg05_,NORMAL ;4
audio mg06_,NORMAL ;5
endif
endif
startup:
;
; E01 ================================================================
;
jsr dspoff
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
read data1
cdplay audio1,0
_@pe_bank #6
_@sp_bank #5,96,0,0,0
memcpy pal_bg,pal_work,$20
memcpy pal_sp,pal_work+512,$20
inc pal_flg
jsr win_flat
jsr dspon
_@wait 60*20,_a99
;
; E02 ================================================================
;
jsr dspoff
mapreg 4,$3a
mapreg 6,$3c
trans $8000,$6000,$2000,MV
trans $c000,$5000,$2000,MV
jsr sat_clr
_@bg_bank #6,0,0
_@anime_start #$3b,0,0,128,0
memcpy pal_bg,pal_work+512*2,$20
memcpy pal_sp,pal_work+512*3,$20
inc pal_flg
jsr win_on
jsr dspon
_@anime_wait _a99
cdwait _a99
;
; E03 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
read data2
mapreg 4,$3d
mapreg 5,$3e
mapreg 6,$3f
read data3
read data4
cdplay audio1,1
jsr dspoff
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$1000,$2000*2,MV
_@bg_bank #1,0,0
inc animate_bnum
_@anime_start #$3a,0,0,128,0
memcpy pal_bg,pal_work,$20
memcpy pal_sp,pal_work+512,$20
inc pal_flg
jsr vsync
jsr dspon
_@anime_wait _a99
stz animate_bnum
;
; E04 ================================================================
;
jsr dspoff
mapreg 5,$3e
mapreg 6,$3f
trans $a000,$1000,$2000*2,MV
jsr sat_clr
inc animate_bnum
_@bg_bank #7,0,0
_@anime_start #$3d,0,0,128,0
memcpy pal_bg,pal_work+512*2,$20
memcpy pal_sp,pal_work+512*3,$20
inc pal_flg
jsr vsync
jsr dspon
_@anime_wait _a99
cdwait _a99
stz animate_bnum
;
; E05 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
read data5
jsr dspoff
trans $0000,$1000,$2000*5,AV
jsr sat_clr
_@bg_bank #1,0,0
_@sp_bank #5,0,0,1,0
;; inc animate_bnum
_@anime_start #$3a,0,0,128,1
memcpy pal_bg,pal_work+512*4,$20
memcpy pal_sp,pal_work+512*5,$40
inc pal_flg
jsr vsync
jsr dspon
_@wait 60,_a99
_@anime_stop
;; stz animate_bnum
;
; E06 ================================================================
;
cdplay audio1,2
jsr dspoff
trans $a000,$6000,$2000,AV
trans $c000,$1000,$2000*2,AV
jsr sat_clr
_@bg_bank #6,0,0
inc animate_bnum
_@anime_start #$3b,0,0,128,1
memcpy pal_bg,pal_work+512*6,$20
memcpy pal_sp,pal_work+512*7,$20
inc pal_flg
jsr vsync
jsr dspon
_@wait 60,_a99
_@anime_stop
stz animate_bnum
;
; E07 ================================================================
;
jsr dspoff
mapreg 5,$3e
mapreg 6,$3f
trans $a000,$1000,$2000*2,MV
jsr sat_clr
_@bg_bank #7,0,0
inc animate_bnum
_@anime_start #$3c,0,0,128,0
memcpy pal_bg,pal_work+512*2,$20
memcpy pal_sp,pal_work+512*3,$20
inc pal_flg
jsr vsync
jsr dspon
_@anime_wait _a99
stz animate_bnum
;
; E08 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
read data6
mapreg 4,$3d
mapreg 5,$3e
mapreg 6,$3f
read data7
jsr dspoff
mapreg 4,$3a
trans $8000,$6000,$2000,MV
trans $0000,$1000,$2000*5,AV
jsr sat_clr
_@bg_bank #6,0,0
inc animate_bnum
_@anime_start #$3b,0,0,128,0
memcpy pal_bg,pal_work,$20
memcpy pal_sp,pal_work+512,$20
inc pal_flg
jsr vsync
jsr dspon
_@anime_wait _a99
_@anime_start #$3c,0,0,128,0
_@anime_wait _a99
stz animate_bnum
;
; E09 ================================================================
;
cdplay audio1,3
jsr dspoff
mapreg 4,$3d
trans $8000,$7000,$2000,MV
trans $a000,$1000,$2000*2,AV
jsr sat_clr
_@bg_bank #7,0,0
inc animate_bnum
_@anime_start #$3e,0,0,128,0
memcpy pal_bg,pal_work+512*2,$20
memcpy pal_sp,pal_work+512*3,$20
inc pal_flg
jsr vsync
jsr dspon
_@anime_wait _a99
cdwait _a99
stz animate_bnum
;
; E10 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
read data8
mapreg 4,$3d
mapreg 5,$3e
mapreg 6,$3f
read data9
jsr dspoff
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$1000,$2000*2,MV
jsr sat_clr
moviw bgy1,128
_@bg_bank #5,0,0
_@bg_bank #6,0,16
_@anime_start #$3a,0,0,128,1
memcpy pal_bg,pal_work,$20
memcpy pal_sp,pal_work+512,$20
inc pal_flg
jsr vsync
jsr win_on
jsr dspon
_@sprscrl_start 0,32,0,1,2
_@bgscrl_start 0,-1,2
_scrl_lp_E10:
_@wait 2,_a99
incw animate_y
cmpiw bgy1,0
bne _scrl_lp_E10
_@sprscrl_stop
_@bgscrl_stop
_@wait 30,_a99
_@anime_stop
;
; E11 ================================================================
;
cdplay audio1,4
jsr dspoff
jsr sat_clr
stzw bgy1
_@bg_bank #4,0,0
memcpy pal_bg,pal_work+512*2,$20
inc pal_flg
jsr dspon
_@wait 30,_a99
_@palc_start pal_bg,pal_work+512*2,pal_work+512*2+$a0,4
_@wait 4*(6-1),_a99
_@palc_stop
_@wait 4,_a99
memcpy pal_bg,pal_work+512*2+$80,$20
inc pal_flg
_@wait 30,_a99
;
; E12 ================================================================
;
jsr dspoff
mapreg 4,$3d
mapreg 5,$3e
mapreg 6,$3f
trans $a000,$1000,$2000*2,MV
inc animate_bnum
_@anime_start #$3d,0,0,128,0
memset pal_bg,zero,$20
memcpy pal_sp,pal_work+512*3,$40
inc pal_flg
jsr dspon
_@anime_wait _a99
stz animate_bnum
;
; E13 ================================================================
;
trans $0000,$4000,$2000*4,AV
jsr dspoff
trans $8000,$1000,$2000,AV
moviw bgx1,64
moviw bgy1,128
jsr sat_clr
_@pe_bank #4
memcpy pal_bg,pal_work+512*4,$20
memcpy pal_sp,pal_work+512*5,$20
inc pal_flg
jsr dspon
_@bgscrl_start 0,-1,2
_scrl_lp_E13:
_@wait 1,_a99
cmpiw bgy1,0
bne _scrl_lp_E13
_@bgscrl_stop
_@sp_bank #1,0,128,0,0
_@sprscrl_start 0,16,0,-1,2
_scrl_lp_E13b:
_@wait 1,_a99
cmpiw sprscrl_count,128
bne _scrl_lp_E13b
_@sprscrl_stop
_@palc_start pal_bg,pal_work+512*4,pal_work+512*4+$c0,4
_@wait 4*(7-1),_a99
_@palc_stop
_@wait 4,_a99
memcpy pal_bg,pal_work+512*4+$a0,$20
inc pal_flg
_@wait 60,_a99
cdwait _a99
;
; A14 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
read data10
cdplay audio1,5
jsr dspoff
trans $0000,$4000,$2000*4,AV
sei
mapreg 5,$3b
trans $a000,$1000,$2000,MV
cli
moviw bgx1,64
moviw bgy1,128
_@pe_bank #4,0,0
_@sp_bank #1,128,0,0,0
_@palc_start pal_bg,pal_work+512*6,pal_work+512*6+$20,2
memcpy pal_sp,pal_work+512*7,$20
inc pal_flg
jsr dspon
_@sprscrl_start 0,16,-1,0,4
_@bgscrl_start 0,-1,4
_scrl_lp_E14:
_@wait 1,_a99
cmpiw bgy1,24
bne _scrl_lp_E14
_@sprscrl_stop
_@bgscrl_stop
_@wait 60,_a99
cdwait _a99
;
; A99 ================================================================
;
jsr dspoff
jsr bgpal_clr
jsr sppal_clr
jsr sat_clr
_a99:
jsr all_done
;
; save common area
;
sei
clx
_move_lp:
lda $3f00,x
sta $2000,x
inx
bne _move_lp
;
; call title prog
;
CDEXEC AXE_BIN,$4000,1
;
endChunk 3#
;
; ENDING
;
include macro.h
include visual.h
include biosw.h
include c62.h
include uty.h
include inf_f.h
;
stage equ $3f00
player equ $3f01
mode equ $3ffe
;
public entry
;
seg dseg
pal_work ds 4096+512
seg cseg
entry:
jmp startup
ifdef tyris
data1:
; data C1_PCB,pal_work,1,LOCAL
; data C1_PBB,$6000,4*2,VRAM
; ;mapreg 4,$3a
; data C1A_CAB,$8000,4*1,LOCAL
; data C1B_CCB,pal_work+512,1,LOCAL
; data C1B_CSB,$2000,4*1,VRAM
; data C1C_CSB,$3000,4*1,VRAM
; data C1D_CSB,$4000,4*1,VRAM
; data C1E_CSB,$5000,4*1,VRAM
; data T1T_CCB,pal_work+512+$20,1,LOCAL
; data T1T_CSB,$1000,4*1,VRAM
data tc001_,pal_work,2,LOCAL
;mapreg 4,$3a
data ta001_,$8000,4*1,LOCAL
data tv001_,$1000,4*7,VRAM
enddata
data2:
; ;mapreg 4,$3d
; ;mapreg 5,$3e
; ;mapreg 6,$3f
; data C2_PCB,pal_work+512*2,1,LOCAL
; data C2_PBB,$0000,4*4,ADPCM
; data T2A_CAB,$8000,4*1,LOCAL
; data T2B_CCB,pal_work+512*3,1,LOCAL
; data T2B_CSB,$a000,4*1,LOCAL
; data T2C_CSB,$c000,4*1,LOCAL
;mapreg 4,$3d
;mapreg 5,$3e
;mapreg 6,$3f
data ta002_,$8000,4*1,LOCAL
data tv002_,$0000,4*4,ADPCM
data tv002b_,$a000,4*2,LOCAL
enddata
data3:
; ;mapreg 4,$3a
; ;mapreg 5,$3b
; ;mapreg 6,$3c
; data C3_CCB,pal_work,1,LOCAL
; data C4_CCB,pal_work+512,1,LOCAL
; data C4A_CCB,pal_work+512*2,1,LOCAL
; data C3_CBB,$8000,4*1,LOCAL
; data C4_CBB,$a000,4*1,LOCAL
; data C4A_CSB,$c000,4*1,LOCAL
data tc003_,pal_work,2,LOCAL
data tv003_,$8000,4*3,LOCAL
enddata
data4:
; ;mapreg 4,$3d
; ;mapreg 5,$3e
; data t5_CCB,pal_work+512*3,1,LOCAL
; data t5B_CCB,pal_work+512*4,1,LOCAL
; data t5_CBB,$8000,4*1,LOCAL
; data t5A_CAB,$a000,4*1,LOCAL
; data t5B_CSB,$0000,4*1,ADPCM
; data t5C_CSB,$2000,4*1,ADPCM
; data t5D_CSB,$4000,4*1,ADPCM
; data t5D_CSB,$6000,4*1,ADPCM
data tv005_,$8000,4*1,LOCAL
data ta005_,$a000,4*1,LOCAL
data tv005b_,$0000,4*4,ADPCM
enddata
data5:
; data T5_CCB,pal_work,1,LOCAL
; data T7B_CCB,pal_work+512,1,LOCAL
; data T5_CBB,$7000,4*1,VRAM
; ;mapreg 4,$3a
; ;mapreg 5,$3b
; ;mapreg 6,$3c
; data T7A_CAB,$8000,4*1,LOCAL
; data T7B_CSB,$a000,4*1,LOCAL
; data T7C_CSB,$c000,4*1,LOCAL
data tc007_,pal_work,2,LOCAL
data ta007_,$8000,4*1,LOCAL
data tv007_,$a000,4*2,LOCAL
enddata
data6:
; ;mapreg 4,$3d
; ;mapreg 5,$3e
; data T8_CCB,pal_work+512*2,1,LOCAL
; data T8B_CCB,pal_work+512*3,1,LOCAL
; data T8_CBB,$8000,4*1,LOCAL
; data T8A_CAB,$a000,4*1,LOCAL
; data T8B_CSB,$0000,4*1,ADPCM
; data T8C_CSB,$2000,4*1,ADPCM
; data T8D_CSB,$4000,4*1,ADPCM
; data T8E_CSB,$6000,4*1,ADPCM
; data T8E_CSB,$8000,4*1,ADPCM
data tv008_,$8000,4*1,LOCAL
data ta008_,$a000,4*1,LOCAL
data tv008b_,$0000,4*5,ADPCM
; data T10A_CAB,$a000,4*1,ADPCM
; data T10B_CCB,pal_work+512*4,1,LOCAL
; data T10B_CSB,$c000,4*1,ADPCM
; data T10C_CSB,$e000,4*1,ADPCM
data ta010_,$a000,4*1,ADPCM
data tv010_,$c000,4*2,ADPCM
enddata
data7:
; data C11_PCB,pal_work,1,LOCAL
; data T11A_CCB,pal_work+512,1,LOCAL
; data C12B_CCB,pal_work+512*2,1,LOCAL
; data C11_PBB,$5000,4*2,VRAM
; data T11A_CSB,$4000,4*1,VRAM
; ;mapreg 4,$3a
; ;mapreg 5,$3b
; ;mapreg 6,$3c
; data C12A_CAB,$8000,4*1,LOCAL
; data C12B_CSB,$a000,4*1,LOCAL
; data C12C_CSB,$c000,4*1,LOCAL
data tc011_,pal_work,2,LOCAL
data tv011_,$4000,4*3,VRAM
data ta012_,$8000,4*1,LOCAL
data tv012_,$a000,4*2,LOCAL
enddata
data8:
; data C14_PCB,pal_work+512*3,1,LOCAL
; data T14B_CCB,pal_work+512*4,1,LOCAL
; data C14_PBB,$0000,4*2,ADPCM
; ;mapreg 4,$3d
; ;mapreg 5,$3e
; ;mapreg 6,$3f
; data T14A_CAB,$8000,4*1,LOCAL
; data T14B_CSB,$a000,4*1,LOCAL
; data T14C_CSB,$c000,4*1,LOCAL
data tv014_,$0000,4*2,ADPCM
data ta014_,$8000,4*1,LOCAL
data tv014b_,$a000,4*2,LOCAL
enddata
data9:
; data C15_PCB,pal_work,1,LOCAL
; data t16_PCB,pal_work+512,1,LOCAL
; data t17_CCB,pal_work+512*2,1,LOCAL
; data t18_PCB,pal_work+512*3,1,LOCAL
; data C15_PBB,$6000,4*2,VRAM
; data t16_PBB,$4000,4*2,VRAM
; data t17_CBB,$3000,4*1,VRAM
; data t18_PBB,$0000,4*4,ADPCM
data tc015_,pal_work,2,LOCAL
data tv015_,$6000,4*2,VRAM
data tv016_,$3000,4*3,VRAM
data tv018_,$0000,4*4,ADPCM
enddata
endif
ifdef battler
data1:
data bc001_,pal_work,2,LOCAL
;mapreg 4,$3a
data ba001_,$8000,4*1,LOCAL
data bv001_,$1000,4*7,VRAM
enddata
data2:
;mapreg 4,$3d
;mapreg 5,$3e
;mapreg 6,$3f
data ba002_,$8000,4*1,LOCAL
data bv002_,$0000,4*4,ADPCM
data bv002b_,$a000,4*2,LOCAL
enddata
data3:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data bc003_,pal_work,2,LOCAL
data bv003_,$8000,4*3,LOCAL
enddata
data4:
;mapreg 4,$3d
;mapreg 5,$3e
data bv005_,$8000,4*1,LOCAL
data ba005_,$a000,4*1,LOCAL
data bv005b_,$0000,4*4,ADPCM
enddata
data5:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data bc007_,pal_work,2,LOCAL
data ba007_,$8000,4*1,LOCAL
data bv007_,$a000,4*2,LOCAL
enddata
data6:
;mapreg 4,$3d
;mapreg 5,$3e
data bv008_,$8000,4*1,LOCAL
data ba008_,$a000,4*1,LOCAL
data bv008b_,$0000,4*5,ADPCM
data ba010_,$a000,4*1,ADPCM
data bv010_,$c000,4*2,ADPCM
enddata
data7:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data bc011_,pal_work,2,LOCAL
data bv011_,$4000,4*3,VRAM
data ba012_,$8000,4*1,LOCAL
data bv012_,$a000,4*2,LOCAL
enddata
data8:
;mapreg 4,$3d
;mapreg 5,$3e
;mapreg 6,$3f
data bv014_,$0000,4*2,ADPCM
data ba014_,$8000,4*1,LOCAL
data bv014b_,$a000,4*2,LOCAL
enddata
data9:
data bc015_,pal_work,2,LOCAL
data bv015_,$6000,4*2,VRAM
data bv016_,$3000,4*3,VRAM
data bv018_,$0000,4*4,ADPCM
enddata
endif
ifdef thunder
data1:
data gc001_,pal_work,2,LOCAL
;mapreg 4,$3a
data ga001_,$8000,4*1,LOCAL
data gv001_,$1000,4*7,VRAM
enddata
data2:
;mapreg 4,$3d
;mapreg 5,$3e
;mapreg 6,$3f
data ga002_,$8000,4*1,LOCAL
data gv002_,$0000,4*4,ADPCM
data gv002b_,$a000,4*2,LOCAL
enddata
data3:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data gc003_,pal_work,2,LOCAL
data gv003_,$8000,4*3,LOCAL
enddata
data4:
;mapreg 4,$3d
;mapreg 5,$3e
data gv005_,$8000,4*1,LOCAL
data ga005_,$a000,4*1,LOCAL
data gv005b_,$0000,4*4,ADPCM
enddata
data5:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data gc007_,pal_work,2,LOCAL
data ga007_,$8000,4*1,LOCAL
data gv007_,$a000,4*2,LOCAL
enddata
data6:
;mapreg 4,$3d
;mapreg 5,$3e
data gv008_,$8000,4*1,LOCAL
data ga008_,$a000,4*1,LOCAL
data gv008b_,$0000,4*5,ADPCM
data ga010_,$a000,4*1,ADPCM
data gv010_,$c000,4*2,ADPCM
enddata
data7:
;mapreg 4,$3a
;mapreg 5,$3b
;mapreg 6,$3c
data gc011_,pal_work,2,LOCAL
data gv011_,$4000,4*3,VRAM
data ga012_,$8000,4*1,LOCAL
data gv012_,$a000,4*2,LOCAL
enddata
data8:
;mapreg 4,$3d
;mapreg 5,$3e
;mapreg 6,$3f
data gv014_,$0000,4*2,ADPCM
data ga014_,$8000,4*1,LOCAL
data gv014b_,$a000,4*2,LOCAL
enddata
data9:
data gc015_,pal_work,2,LOCAL
data gv015_,$6000,4*2,VRAM
data gv016_,$3000,4*3,VRAM
data gv018_,$0000,4*4,ADPCM
enddata
endif
ifdef audio
audio1:
ifdef tyris
audio et01_,NORMAL ;0
audio et02_,NORMAL ;1
audio et03_,NORMAL ;2
audio et04_,NORMAL ;3
audio et05_,NORMAL ;4
audio ending_,REPEAT ;5
endif
ifdef battler
audio eb01_,NORMAL ;0
audio eb02_,NORMAL ;1
audio eb03_,NORMAL ;2
audio eb04_,NORMAL ;3
audio eb05_,NORMAL ;4
audio ending_,REPEAT ;5
endif
ifdef thunder
audio eg01_,NORMAL ;0
audio eg02_,NORMAL ;1
audio eg03_,NORMAL ;2
audio eg04_,NORMAL ;3
audio eg05_,NORMAL ;4
audio ending_,REPEAT ;5
endif
endif
startup:
;
; F01 ================================================================
;
jsr dspoff
mapreg 4,$3a
read data1
mapreg 4,$3d
mapreg 5,$3e
mapreg 6,$3f
read data2
cdplay audio1,0
_@pe_bank #6
_@sp_bank #1,0,0,1,256
inc animate_bnum
_@anime_start #$3a,128,0,128,0
memcpy pal_bg,pal_work,$20
memcpy pal_sp,pal_work+512,$40
inc pal_flg
jsr win_flat
jsr vsync
jsr dspon
_@anime_wait _a99
stz animate_bnum
;
; F02 ================================================================
;
jsr dspoff
trans $0000,$4000,$2000*4,AV
mapreg 4,$3e
mapreg 6,$3f
trans $a000,$2000,$2000*2,MV
jsr sat_clr
moviw bgx1,64
moviw bgy1,128
_@pe_bank #4,0,0
;; inc animate_bnum
_@anime_start #$3d,0,-128,128,0
;;; _@anime_start #$3d,0,-64,128,0
_@wait 2,_a99
_@anime_stop
memcpy pal_bg,pal_work+512*2,$20
memcpy pal_sp,pal_work+512*3,$20
inc pal_flg
jsr win_on
jsr dspon
_@sprscrl_start 16,16,0,1,2
_@bgscrl_start 0,-1,2
_scrl_lp_F02:
_@wait 1,_a99
cmpiw bgy1,0
bne _scrl_lp_F02
_@sprscrl_stop
_@bgscrl_stop
_@anime_start #$3d,0,0,128,0
_@anime_wait _a99
;; stz animate_bnum
_@wait 60,_a99
cdwait _a99
;
; F03 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
read data3
mapreg 4,$3d
mapreg 5,$3e
read data4
cdplay audio1,1
jsr dspoff
mapreg 4,$3a
trans $8000,$7000,$2000,MV
jsr sat_clr
stzw bgx1
stzw bgy1
_@bg_bank #7,0,0
memcpy pal_bg,pal_work,$20
inc pal_flg
jsr vsync
jsr dspon
_@wait 60,_a99
;
; F04 ================================================================
;
jsr dspoff
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$6000,$2000*2,MV
jsr sat_clr
_@bg_bank #6,0,0
_@sp_bank #7,0,0,0,0
memcpy pal_bg,pal_work+512,$20
memcpy pal_sp,pal_work+512*2,$20
inc pal_flg
jsr vsync
jsr dspon
_@wait 60*5,_a99
;
; E05 ================================================================
;
jsr dspoff
mapreg 4,$3d
mapreg 5,$3e
trans $8000,$7000,$2000,MV
trans $0000,$1000,$2000*4,AV
jsr sat_clr
_@bg_bank #7,0,0
inc animate_bnum
_@anime_start #$3e,0,0,128,0
memcpy pal_bg,pal_work+512*3,$20
memcpy pal_sp,pal_work+512*4,$20
inc pal_flg
jsr vsync
jsr dspon
_@anime_wait _a99
stz animate_bnum
;
; E06 ================================================================
;
jsr dspoff
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$5000,$2000*2,MV
jsr sat_clr
_@bg_bank #5,0,0
_@sp_bank #6,0,0,0,0
memcpy pal_bg,pal_work+512,$20
memcpy pal_sp,pal_work+512*2,$20
inc pal_flg
jsr vsync
jsr dspon
_@wait 60*5,_a99
_@palc_start pal_sp,pal_work+512*2,pal_work+512*2+$80,8
_@wait 8*(5-1),_a99
_@palc_stop
_@wait 60,_a99
_@palc_start pal_sp,pal_work+512*2+$a0,pal_work+512*2+$100,8
_@wait 8*(4-1),_a99
_@palc_stop
_@wait 8,_a99
_@fadeup_start pal_bg,pal_sp,1,8
_@fadeup_wait _a99
jsr sat_clr
_@fadedwn_start pal_bg,pal_work+512,pal_sp,pal_work+512*2,1,4
_@fadedwn_wait _a99
cdwait _a99
;
; E07 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
read data5
mapreg 4,$3d
mapreg 5,$3e
read data6
cdplay audio1,2
jsr dspoff
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$1000,$2000*2,MV
jsr sat_clr
_@bg_bank #7,0,0
inc animate_bnum
_@anime_start #$3a,0,0,128,0
memcpy pal_bg,pal_work,$20
memcpy pal_sp,pal_work+512,$20
inc pal_flg
jsr vsync
jsr dspon
_@anime_wait _a99
stz animate_bnum
;
; E08 ================================================================
;
jsr dspoff
mapreg 4,$3d
trans $8000,$1000,$2000,MV
trans $0000,$2000,$2000*5,AV
jsr sat_clr
_@bg_bank #1,0,0
inc animate_bnum
_@anime_start #$3e,0,0,128,0
memcpy pal_bg,pal_work+512*2,$20
memcpy pal_sp,pal_work+512*3,$20
inc pal_flg
jsr vsync
jsr dspon
_@anime_wait _a99
stz animate_bnum
;
; E09 ================================================================
;
; nop
;
; E10 ================================================================
;
jsr dspoff
mapreg 4,$3a
trans $a000,$8000,$2000,AM
trans $c000,$1000,$2000*2,AV
jsr sat_clr
_@bg_bank #7,0,0
_@anime_start #$3a,0,0,128,0
memcpy pal_bg,pal_work,$20
memcpy pal_sp,pal_work+512*4,$20
inc pal_flg
jsr vsync
jsr dspon
_@anime_wait _a99
cdwait _a99
;
; E11 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
read data7
mapreg 4,$3d
mapreg 5,$3e
mapreg 6,$3f
read data8
cdplay audio1,3
jsr dspoff
jsr sat_clr
stzw bgy1
_@pe_bank #5
_@sp_bank #4,0,0,0,0
memcpy pal_bg,pal_work,$20
memcpy pal_sp,pal_work+512,$20
inc pal_flg
jsr dspon
_@sprscrl_start 0,16,-1,0,4
_@bgscrl_start 1,0,4
_scrl_lp_F11:
_@wait 1,_a99
cmpiw bgx1,128
bne _scrl_lp_F11
_@sprscrl_stop
_@bgscrl_stop
_@wait 60*6,_a99
;
; E12 ================================================================
;
jsr dspoff
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$1000,$2000*2,MV
stzw bgx1
stzw bgy1
_@sp_bank #1,0,0,0,128
_@anime_start #$3a,0,0,0,0
memset pal_bg,zero,$20
memcpy pal_sp,pal_work+512*2,$40
inc pal_flg
jsr dspon
_@anime_wait _a99
_@wait 60*3,_a99
;
; E13 ================================================================
;
jsr dspoff
jsr sat_clr
stzw bgy1
_@pe_bank #5
_@sp_bank #4,0,0,0,0
memcpy pal_bg,pal_work,$20
memcpy pal_sp,pal_work+512,$20
inc pal_flg
jsr win_flat
jsr dspon
_@wait 60*3,_a99
;
; A14 ================================================================
;
jsr dspoff
trans $0000,$6000,$2000*2,AV
mapreg 5,$3e
mapreg 6,$3f
trans $a000,$1000,$2000*2,MV
jsr sat_clr
_@pe_bank #6,0,0
_@anime_start #$3d,128,0,128,0
jsr vsync
_@anime_stop
memcpy pal_bg,pal_work+512*3,$20
memcpy pal_sp,pal_work+512*4,$20
inc pal_flg
jsr win_on
jsr dspon
_@sprscrl_start 16,16,-1,0,2
_@bgscrl_start 1,0,2
_scrl_lp_F14:
_@wait 1,_a99
cmpiw bgx1,128
bne _scrl_lp_F14
_@sprscrl_stop
_@bgscrl_stop
_@anime_start #$3d,0,0,128,0
_@anime_wait _a99
cdwait _a99
_@fadeout_start pal_bg,pal_sp,1,8
_@fadeout_wait _a99
;
; FIN ================================================================
;
jsr dspoff
read data9
cdplay audio1,4
jsr sat_clr
stzw bgx1
_@pe_bank #6
memcpy pal_bg,pal_work,$20
inc pal_flg
jsr win_on
jsr dspon
_@bgscrl_start 1,0,4
_scrl_lp_FIN1:
_@wait 1,_a99
cmpiw bgx1,128
bne _scrl_lp_FIN1
_@bgscrl_stop
_@wait 60*5,_a99
jsr dspoff
_@pe_bank #4
memcpy pal_bg,pal_work+512,$20
inc pal_flg
jsr dspon
_@bgscrl_start -1,0,4
_scrl_lp_FIN2:
_@wait 1,_a99
cmpiw bgx1,0
bne _scrl_lp_FIN2
_@bgscrl_stop
_@wait 60*5,_a99
jsr dspoff
_@bg_bank #3,0,0
memcpy pal_bg,pal_work+512*2,$20
inc pal_flg
jsr dspon
_@wait 60*18,_a99
jsr dspoff
trans $0000,$4000,$2000*4,AV
_@pe_bank #4
memcpy pal_bg,pal_work+512*3,$20
inc pal_flg
jsr win_off
jsr dspon
_@wait 60*5,_a99
_@palc_start pal_bg,pal_work+512*3,pal_work+512*3+$80,8
_@wait 8*(5-1),_a99
_@palc_stop
cdwait _a99
cdplay audio1,5
_fin_lp:
_@wait 1,_a99
bra _fin_lp
;
; A99 ================================================================
;
jsr dspoff
jsr bgpal_clr
jsr sppal_clr
jsr sat_clr
_a99:
jsr all_done
;
; save common area
;
sei
clx
_move_lp:
lda $3f00,x
sta $2000,x
inx
bne _move_lp
;
; call title prog
;
CDEXEC GA_BIN,$4000,1
;
endChunk 4#
;
; TITLE
;
include macro.h
include visual.h
include biosw.h
include c62.h
include uty.h
include inf_t.h
;
player equ $3f00
Min_pl equ $00
Max_pl equ $02
;
_Max_ = 10
;
public entry
;
seg dseg
sppal_work ds 2048+$100
bgpal_work ds 2048+$100
seg cseg
entry:
jmp startup
data1: ;MAPREG 4,$3a
data TCOLOR_CCB,bgpal_work,1,LOCAL
data SORA1_CBB,$8000,4*1,LOCAL
data TITLEX1_CSB,$0000,4*4,ADPCM
;MAPREG 5,$3b
;MAPREG 6,$3c
data TITLEX2_CSB,$a000,4*2,LOCAL
enddata
data2: data TITLEX3_CBB,$8000,4*4,ADPCM
;MAPREG 4,$3d
;MAPREG 5,$3e
data ROGOX1_CSB,$8000,4*2,LOCAL
enddata
data3: ;MAPREG 4,$3a
;MAPREG 5,$3b
;MAPREG 6,$3c
data SX1_CCB,sppal_work,1,LOCAL
data SX1_CSB,$8000,4*3,LOCAL
enddata
data4: ;MAPREG 4,$3d
data SX2_CSB,$8000,4,LOCAL
enddata
ifdef audio
audio1:
audio opening_,REPEAT
;; audio title_,REPEAT
audio opening_,REPEAT
endif
startup:
;
; T01 ================================================================
;
jsr dspoff
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
read data1
mapreg 4,$3d
mapreg 5,$3e
read data2
cdplay audio1,0
memcpy sppal_work,bgpal_work+512,512
memcpy bgpal_work+$40,sppal_work,512
memcpy sppal_work+$20,bgpal_work+1024,512
mapreg 4,$3a
trans $8000,$1000,$2000,MV ;bg/sora
trans $0000,$4000,$2000*4,AV ;sp/title1~title4
_@bg_bank #1,00,00
_@bg_bank #1,16,00
_@bg_bank #1,00,16
_@bg_bank #1,16,16
_@sp_bank #4, 0,128,0,64*0
_@sp_bank #5,128,128,0,64*1
_@sp_bank #6, 0,256,0,64*2
_@sp_bank #7,128,256,0,64*3
memset pal_bg,zero,$60
memset pal_sp,zero,$60
inc pal_flg
jsr dspon
_@fadein_start pal_bg,bgpal_work,pal_sp,sppal_work,3,4
_@fadein_wait _skip
_@sprscrl_start 0,32,0,-1,1
_@bgscrl_start 0,-8,1
_sprscrl_lp:
_@wait 1,_skip
cmpiw sprscrl_count,128
bne _sprscrl_lp
_@sprscrl_stop
_@wait 60*1,_skip
_@fadeout_start pal_bg,pal_bg+$20,1,10
ldx #-8
_scrl_lp:
stx bgscrl_y
_@wait 10,_skip
inx
bne _scrl_lp
_@fadeout_wait _skip
_@bgscrl_stop
stzw bgy1
jsr vsync
mapreg 6,$3f
trans $a000,$1000,$2000,AV
trans $c000,$2000,$2000,AV
trans $e000,$3000,$2000,AV
trans $8000,$0000,$1000,AV
memcpy pal_bg,bgpal_work+$40,$20
stzw pal_bg
inc pal_flg
jsr vsync
jsr sat_clr
jsr vsync
mapreg 4,$3d
trans $8000,$6000,$2000,MV
mapreg 4,$3d
trans $0000,$8000,$2000,AM
mapreg 6,$3f
trans $2000,$c000,$2000,AM
moviw src,rogo_org
moviw dst,rogo_tbl
ldy #8*_Max_
jsr movsb
moviw x_tbl_ptr,x_tbl-2*(_Max_-1)
moviw y_tbl_ptr,y_tbl-2*(_Max_-1)
moviw fb_tbl_ptr,fb_tbl-(_Max_-1)
lda #1
sta rogo_counter
lda #100
sta counter
_change_x:
movmw src,x_tbl_ptr
moviw dst,xy
ldy #(2*_Max_)
jsr movsb
addmw rogo_tbl+(8*0)+2,xy+$12
addmw rogo_tbl+(8*1)+2,xy+$10
addmw rogo_tbl+(8*2)+2,xy+$0e
addmw rogo_tbl+(8*3)+2,xy+$0c
addmw rogo_tbl+(8*4)+2,xy+$0a
addmw rogo_tbl+(8*5)+2,xy+$08
stzw rogo_tbl+(8*6)+2
addmw rogo_tbl+(8*7)+2,xy+$04
addmw rogo_tbl+(8*8)+2,xy+$02
addmw rogo_tbl+(8*9)+2,xy+$00
_chenge_y:
movmw src,y_tbl_ptr
moviw dst,xy
ldy #(2*_Max_)
jsr movsb
submw rogo_tbl+(8*0),xy+$12
submw rogo_tbl+(8*1),xy+$10
submw rogo_tbl+(8*2),xy+$0e
submw rogo_tbl+(8*3),xy+$0c
submw rogo_tbl+(8*4),xy+$0a
submw rogo_tbl+(8*5),xy+$08
stzw rogo_tbl+(8*6)
submw rogo_tbl+(8*7),xy+$04
submw rogo_tbl+(8*8),xy+$02
submw rogo_tbl+(8*9),xy+$00
_change_fb:
movmw src,fb_tbl_ptr
moviw dst,fb
ldy #(_Max_)
jsr movsb
mov rogo_tbl+(8*0)+6,fb+$09
mov rogo_tbl+(8*1)+6,fb+$08
mov rogo_tbl+(8*2)+6,fb+$07
mov rogo_tbl+(8*3)+6,fb+$06
mov rogo_tbl+(8*4)+6,fb+$05
mov rogo_tbl+(8*5)+6,fb+$04
stzw rogo_tbl+(8*6)+6
mov rogo_tbl+(8*7)+6,fb+$02
mov rogo_tbl+(8*8)+6,fb+$01
mov rogo_tbl+(8*9)+6,fb+$00
moviw src,rogo_tbl
moviw dst,sp_buf
lda rogo_counter
asl a
asl a
asl a
tay
jsr movsb
_put_spr:
inc spr_flg
_@wait 2,_skip
incw x_tbl_ptr
incw x_tbl_ptr
incw y_tbl_ptr
incw y_tbl_ptr
incw fb_tbl_ptr
lda rogo_counter
cmp #10
beq _go_next
inc rogo_counter
_go_next:
dec counter
jne _change_x
_@wait 30,_skip
sei
mapreg 5,$3b
trans $a000,$4000,$2000,MV
mapreg 6,$3c
trans $c000,$5000,$2000,MV
cli
_@sp_bank #4, 0,128,0,128+64*2
_@sp_bank #5,128,128,0,128+64*3
memset sp_buf,zero,256
inc spr_flg
jsr vsync
sei
mapreg 4,$3d
trans $8000,$6000,$2000,MV
mapreg 6,$3f
trans $c000,$7000,$2000,MV
cli
_@sp_bank #6, 0, 0,0,128+64*0
_@sp_bank #7,128, 0,0,128+64*1
memset pal_bg,zero,$20
inc pal_flg
jsr vsync
sei
mapreg 5,$3e
trans $a000,$3000,$2000,MV
mapreg 4,$3a
trans $8000,$1000,$2000,MV
cli
_TELENET:
moviw src,telene_tbl
moviw dst,sp_buf
ldy #8*5
jsr movsb
inc spr_flg
jsr bgon
jsr vsync
_@bg_bank #1,00,00
_@bg_bank #1,16,00
_@bg_bank #1,00,16
_@bg_bank #1,16,16
_@bgscrl_start 0,1,1
_@fadein_start pal_bg,bgpal_work+$20,pal_bg+$20,bgpal_work,3,4
_@fadein_wait _skip
_lplp:
jsr vsync
lda joy
bit #$08
beq _lplp
jsr sat_clr
lda #$0c
jsr cd_fade
_@wait 60*2+30,_member
jmp _member
_skip:
jsr all_done
jsr sat_clr
stzw bgy1
mapreg 4,$3a
trans $8000,$1000,$2000,MV
_@bg_bank #1,00,00
_@bg_bank #1,16,00
_@bg_bank #1,00,16
_@bg_bank #1,16,16
_@bgscrl_start 0,1,1
_@fadein_start pal_bg,bgpal_work+$20,pal_bg+$20,bgpal_work,3,4
_wait_fi: lda fadein_flg
bne _wait_fi
_member:
stz done_flg
jsr sat_clr
jsr vsync
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
read data3
mapreg 4,$3d
read data4
cdplay audio1,1
_1:
mapreg 4,$3d
trans $8000,$2000,$2000,MV
mapreg 4,$3a
trans $8000,$3000,$2000,MV
mapreg 5,$3b
trans $a000,$4000,$2000,MV
mapreg 6,$3c
trans $c000,$5000,$2000,MV
moviw src,select_tbl
moviw dst,sp_buf
ldy #8*(5+7)
jsr movsb
inc spr_flg
memcpy pal_sp,sppal_work,512
jsr vsync
stz done_flg
_@palc_start pal_sp,sppal_work,sppal_work+$100,8
_@sprscrl_start 0,5+7,-16,0,1
_sprscrl_lp2: ;character
jsr vsync
cmpiw sprscrl_count,256/16
bne _sprscrl_lp2
_@sprscrl_stop
moviw src,tyris_tbl
moviw dst,sp_buf+8*(5+7)
ldy #8*4
jsr movsb
inc spr_flg
jsr vsync
_@sprscrl_start 5+7,5+7+4,-8,0,1
_sprscrl_lp3: ;tyris
jsr vsync
cmpiw sprscrl_count,256/8
bne _sprscrl_lp3
_@sprscrl_stop
moviw src,battler_tbl
moviw dst,sp_buf+8*(5+7+4)
ldy #8*4
jsr movsb
inc spr_flg
jsr vsync
_@sprscrl_start 5+7+4,5+7+8,-8,0,1
_sprscrl_lp4: ;battler
jsr vsync
cmpiw sprscrl_count,256/8
bne _sprscrl_lp4
_@sprscrl_stop
moviw src,thunder_tbl
moviw dst,sp_buf+8*(5+7+8)
ldy #8*6
jsr movsb
inc spr_flg
jsr vsync
_@sprscrl_start 5+7+8,5+7+14,-8,0,1
_sprscrl_lp5: ;thunder
jsr vsync
cmpiw sprscrl_count,256/8
bne _sprscrl_lp5
_@sprscrl_stop
_trg_lp: ;wait joypad trigger
jsr vsync
lda joy
bne _trg_lp
stz done_flg
stz player
_main_lp:
memcpy pal_sp+$100,sppal_work+$100,$20*3
lda player
cmp #00
bne _pl1
_pl0:
lda pal_sp+$100+$0d*2
sta pal_sp+$100+$0e*2
lda pal_sp+$100+$0d*2+1
sta pal_sp+$100+$0e*2+1
jmp _read_joy
_pl1:
cmp #01
bne _pl2
lda pal_sp+$120+$0d*2
sta pal_sp+$120+$0e*2
lda pal_sp+$120+$0d*2+1
sta pal_sp+$120+$0e*2+1
jmp _read_joy
_pl2:
cmp #02
bne _read_joy
lda pal_sp+$140+$0d*2
sta pal_sp+$140+$0e*2
lda pal_sp+$140+$0d*2+1
sta pal_sp+$140+$0e*2+1
_read_joy:
inc pal_flg
ldx #10
_wait_joytrg:
jsr vsync
lda joytrg
bne _check_left
dex
bne _wait_joytrg
lda joy
_check_left:
bit #$80
beq _check_right
lda player
dec a
cmp #Min_pl-1
bne _store
lda #Max_pl
jmp _store
_check_right:
bit #$20
beq _check_run
lda player
inc a
cmp #Max_pl+1
bne _store
lda #Min_pl
jmp _store
_check_run:
bit #$08
beq _other
ldx player
lda player_tbl,x
sta player
jmp _T99
_store:
sta player
_other:
jmp _main_lp
;
; T99 ================================================================
;
jsr dspoff
jsr bgpal_clr
jsr sppal_clr
jsr sat_clr
_T99:
jsr all_done
sei
clx
_move_lp:
lda $3f00,x
sta $2000,x
inx
bne _move_lp
CDEXEC VISUAL_BIN,$4000,1
player_tbl:
db $20,$00,$10
;
counter db 0
xy ds 2*10
fb ds 10
x_tbl_ptr dw x_tbl
dw 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
x_tbl:
dw 225,-25,-25,-25,-25,-25,-25,-25,-25,-25
dw 01, 02, 04, 08, 16, 16, 16, 16, 16, 32
dw 32, 16, 16, 16, 16, 16, 08, 04, 02, 01
dw -01,-02,-04,-08,-16,-16,-16,-16,-16,-32
dw -32,-16,-16,-16,-16,-16,-08,-04,-02,-01
dw 01, 02, 04, 08, 16, 16, 16, 16, 16, 32
dw 32, 16, 16, 16, 16, 16, 08, 04, 02, 01
;;; dw -01,-02,-04,-08,-08,-16,-16,-16,-16,-16
; dw -01,-02,-02,-04,-04,-08,-08,-08,-08,-16
; dw -16,-24,-24,-32,-32, 00, 00, 00, 00, 00
dw -01,-02,-04,-08,-16,-16,-16,-16,-16,-24
dw -24,-24,-24,-24,-24,-24,-24,-24,-24,-24
dw -24,-24,-24,-24,-24,-24,-24,-24,-24,-24
y_tbl_ptr dw y_tbl
dw 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
y_tbl:
dw -97, 01, 01, 01, 02, 04, 08, 16, 32, 32
dw 08, 04, 04, 04, 04, 02, 02, 02, 02, 01
dw -01,-02,-02,-02,-02,-04,-04,-04,-04,-08
dw -08,-04,-04,-04,-04,-02,-02,-02,-02,-01
dw 01, 02, 02, 02, 02, 04, 04, 04, 04, 08
dw 08, 04, 04, 04, 04, 02, 02, 02, 02, 01
dw -01,-02,-02,-02,-02,-04,-04,-04,-04,-08
;;; dw -08,-08,-08,-08,-08,-08,-04,-04,-04,-04
; dw -08,-08,-08,-08,-32,-00,-00,-00,-00,-00
; dw 00, 00, 00, 00, 00, 00, 00, 00, 00, 00
dw -08,-04,-04,-04,-04,-02,-02,-02,-02,-01
dw -01,-01,-01,-01,-01,-01,-01,-01,-01,-01
dw -01,-01,-01,-01,-01,-01,-01,-01,-01,-01
fb_tbl_ptr dw fb_tbl
db 81, 81, 81, 81, 81, 81, 81, 81, 81, 81
fb_tbl:
db $81,$81,$81,$81,$81,$81,$81,$81,$81,$81
db $02,$02,$02,$02,$02,$02,$02,$02,$02,$02
db $02,$02,$02,$02,$02,$02,$02,$02,$02,$02
db $81,$81,$81,$81,$81,$81,$81,$81,$81,$81
db $81,$81,$81,$81,$81,$81,$81,$81,$81,$81
db $02,$02,$02,$02,$02,$02,$02,$02,$02,$02
db $02,$02,$02,$02,$02,$02,$02,$02,$02,$02
db $81,$81,$81,$81,$81,$81,$81,$81,$81,$81
db $81,$81,$81,$81,$81,$81,$81,$81,$81,$81
rogo_counter db 1
rogo_org:
dw 64+$40, $10,$0300,$3181 ;G
dw 64+$40, $10,$0310,$3181 ;O
dw 64+$40, $10,$0320,$3181 ;L
dw 64+$40, $10,$0330,$3181 ;D
dw 64+$40, $10,$0340,$3181 ;E
dw 64+$40, $10,$0350,$3181 ;N
dw 64+$40, $10,$0000,$3181 ;
dw 64+$40, $10,$0360,$3181 ;A
dw 64+$40, $10,$0370,$3181 ;X
dw 64+$40, $10,$0340,$3181 ;E
rogo_tbl:
dw 64+$40, $10,$0300,$3181 ;G
dw 64+$40, $10,$0310,$3181 ;O
dw 64+$40, $10,$0320,$3181 ;L
dw 64+$40, $10,$0330,$3181 ;D
dw 64+$40, $10,$0340,$3181 ;E
dw 64+$40, $10,$0350,$3181 ;N
dw 64+$40, $10,$0000,$3181 ;
dw 64+$40, $10,$0360,$3181 ;A
dw 64+$40, $10,$0370,$3181 ;X
dw 64+$40, $10,$0340,$3181 ;E
telene_tbl:
dw 64*3+64, $60,$0180,$1181 ;TE
dw 64*3+64, $80,$0188,$1181 ;LE
dw 64*3+64, $a0,$0190,$1181 ;NE
dw 64*3+64, $c0,$0198,$1181 ;T
dw 64*1+32, $90,$01a0,$1181 ;*
select_tbl:
dw $40+24, $20+$30+256,$0100,$0180 ;SEL
dw $40+24, $20+$50+256,$0104,$0180 ;ECT
dw $40+24, $20+$70+256,$0108,$0180 ; PL
dw $40+24, $20+$90+256,$010c,$0180 ;AYE
dw $40+24, $20+$b0+256,$0110,$0180 ;R
dw $40+$b0, $20+$10+256,$0120,$1180 ;GO
dw $40+$b0, $20+$30+256,$0128,$1180 ;LD
dw $40+$b0, $20+$50+256,$0130,$1180 ;EN
dw $40+$b0, $20+$70+256,$0138,$1180 ; A
dw $40+$b0, $20+$90+256,$0140,$1180 ;XE
dw $40+$b0, $20+$b0+256,$0148,$1180 ;
dw $40+$b0, $20+$d0+256,$0150,$1180 ;
tyris_tbl:
dw $40+$30, $20+$10+256,$0180,$3188 ;
dw $40+$70, $20+$10+256,$0190,$3188 ;
dw $40+$30, $20+$30+256,$01a0,$3188 ;
dw $40+$70, $20+$30+256,$01b0,$3188 ;
battler_tbl:
dw $40+$30, $20+$60+256,$0200,$3189 ;
dw $40+$70, $20+$60+256,$0210,$3189 ;
dw $40+$30, $20+$80+256,$0220,$3189 ;
dw $40+$70, $20+$80+256,$0230,$3189 ;
thunder_tbl:
dw $40+$30, $20+$a0+256,$0280,$318a ;
dw $40+$70, $20+$a0+256,$0290,$318a ;
dw $40+$30, $20+$c0+256,$02a0,$318a ;
dw $40+$70, $20+$c0+256,$02b0,$318a ;
dw $40+$30, $20+$e0+256,$02c0,$318a ;
dw $40+$70, $20+$e0+256,$02d0,$318a ;
;
endChunk 5#
VISUAL_TEST = 0
FINAL_ZONE = 0
GOLDEN_AXE = 1
include inf.h
;
; IPL INFORMATION BLOCK DATA FORMAT (DATA RECORD TOP + 1)
;
if VISUAL_TEST
db SYSTEM_STARTUP_BIN_HI ;$00 ;00 IPLBLK H ;load start record no. of CD
db HIGH(SYSTEM_STARTUP_BIN_LW) ;$00 ;01 IPLBLK M ;load start record no. of CD
db LOW (SYSTEM_STARTUP_BIN_LW) ;$d7 ;02 IPLBLK L ;load start record no. of CD
db SYSTEM_STARTUP_BIN_RL ;1 ;03 IPLBLN ;load block length of CD
db LOW ($4000) ;$00 ;04 IPLSTA L ;program load address L
db HIGH($4000) ;$40 ;05 IPLSTA H ;program load address H
db LOW ($4000) ;$00 ;06 IPLJMP L ;program execute address L
db HIGH($4000) ;$40 ;07 IPLJMP H ;program execute address H
elseif FINAL_ZONE
db fz_fz_BIN_HI ;$00 ;00 IPLBLK H ;load start record no. of CD
db HIGH(fz_fz_BIN_LW) ;$00 ;01 IPLBLK M ;load start record no. of CD
db LOW (fz_fz_BIN_LW) ;$d7 ;02 IPLBLK L ;load start record no. of CD
db fz_fz_BIN_RL ;1 ;03 IPLBLN ;load block length of CD
db LOW ($4000) ;$00 ;04 IPLSTA L ;program load address L
db HIGH($4000) ;$40 ;05 IPLSTA H ;program load address H
db LOW ($4000) ;$00 ;06 IPLJMP L ;program execute address L
db HIGH($4000) ;$40 ;07 IPLJMP H ;program execute address H
elseif GOLDEN_AXE
db ga_BIN_HI ;$00 ;00 IPLBLK H ;load start record no. of CD
db HIGH(ga_BIN_LW) ;$00 ;01 IPLBLK M ;load start record no. of CD
db LOW (ga_BIN_LW) ;$d7 ;02 IPLBLK L ;load start record no. of CD
db ga_BIN_RL ;1 ;03 IPLBLN ;load block length of CD
db LOW ($4000) ;$00 ;04 IPLSTA L ;program load address L
db HIGH($4000) ;$40 ;05 IPLSTA H ;program load address H
db LOW ($4000) ;$00 ;06 IPLJMP L ;program execute address L
db HIGH($4000) ;$40 ;07 IPLJMP H ;program execute address H
endif
;
db 0 ;08 IPLMPR2 ;ipl set mpr2 (+ max_mapping)
db 1 ;09 IPLMPR3 ;ipl set mpr3 (+ max_mapping)
db 2 ;10 IPLMPR4 ;ipl set mpr4 (+ max_mapping)
db 3 ;11 IPLMPR5 ;ipl set mpr5 (+ max_mapping)
db 4 ;12 IPLMPR6 ;ipl set mpr6 (+ max_mapping)
;
db 1 ;13 OPENMODE ;opening mode
;bit76543210
; ||| ||__ data read to vram
; ||| | 0:not read
; ||| | 1:read
; ||| |___ data read to adpcm buff
; ||| 0:not read
; ||| 1:read
; |||_______ bg display
; || 0:disp on
; || 1:disp off
; ||________ adpcm play
; | 0:play
; | 1:not play
; |_________ adpcm play mode
; 0:single
; 1:repeat
;
db reno__HI ;$00 ;14 GRPBLK H ;opening graphic data record no.
db HIGH(reno__LW) ;$00 ;15 GRPBLK M ;opening graphic data record no.
db LOW (reno__LW) ;$d8 ;16 GRPBLK L ;opening graphic data record no.
db reno__RL ;$06 ;17 GRPBLN ;opening graphic data length
db LOW ($1000) ;0 ;18 GRPADR L ;opening graphic data read adrress L
db HIGH($1000) ;$10 ;19 GRPADR H ;opening graphic data read adrress H
;
db 0 ;20 ADPBLK H ;opening ADPCM data record no.
db 0 ;21 ADPBLK M ;opening ADPCM data record no.
db 0 ;22 ADPBLK L ;opening ADPCM data record no.
db 0 ;23 ADPBLN ;opening ADPCM data length
db 0 ;24 ADPRATE ;opening ADPCM sampling rate
;
db 0 ;25 ;(reserve)
db 0 ;26 ;(reserve)
db 0 ;27 ;(reserve)
db 0 ;28 ;(reserve)
db 0 ;29 ;(reserve)
db 0 ;30 ;(reserve)
db 0 ;31 ;(reserve)
;
db 'PC Engine CD-ROM SYSTEM',0 ;(ID string)
db 'Copyright HUDSON SOFT / NEC Home Electronics,Ltd.',0
if VISUAL_TEST
db 'VISUAL TEST ' ;program name (16 bytes)
db ' ' ; (6 bytes)
elseif FINAL_ZONE
db 'FINAL ZONE II ' ;program name (16 bytes)
db ' ' ; (6 bytes)
elseif GOLDEN_AXE
db 'GOLDEN AXE ' ;program name (16 bytes)
db ' ' ; (6 bytes)
endifChunk 6#
;
include \system\macro.h
include \system\visual.h
include \system\biosw.h
include \system\c62.h
include inf_t.h
;
_Max_ = 10
;
public entry
;
seg dseg
sppal_work ds 2048+$100
bgpal_work ds 2048+$100
seg cseg
entry:
call dspoff
call vsync
call bgpal_clr
call sppal_clr
call sat_clr
;
; jmp _GA08_read
;
;
; T01 ================================================================
;
_T01_read:
;1000(v): BG/SORA1.CBB
CDREAD SORA2_PCB,bgpal_work,1,1
CDREAD SORA_PCB,bgpal_work+$20,1,1
CDREAD SORA1_CBB,$1000,4,$ff
;2000(v): SP/TITLE1.CSB
;3000(v): SP/TITLE2.CSB
;4000(v): SP/TITLE3.CSB
;5000(v): SP/TITLE4.CSB
CDREAD TITLE1_CCB,sppal_work,1,1
CDREAD TITLE1_CSB,$2000,4*1,$ff
CDREAD TITLE2_CSB,$3000,4*1,$ff
CDREAD TITLE3_CSB,$4000,4*1,$ff
CDREAD TITLE4_CSB,$5000,4*1,$ff
;6000(v): SP/ROGO2.CSB
CDREAD ROGO2_CCB,sppal_work+$20,1,1
CDREAD ROGO2_CSB,$6000,4*1,$ff
CDREAD ROGO3_CSB,$7000,4*1,$ff
_@bg_bank #1,00,00
_@bg_bank #1,16,00
_@bg_bank #1,00,16
_@bg_bank #1,16,16
_@sp_bank #2, 0,128,0,128+64*0
_@sp_bank #3,128,128,0,128+64*1
_@sp_bank #4, 0,256,0,128+64*2
_@sp_bank #5,128,256,0,128+64*3
memset pal_bg,zero,$60
memset pal_sp,zero,$60
inc pal_flg
call vsync
call dspon
;;; _@fadedwn_start pal_bg,bgpal_work,pal_sp,sppal_work,3,4
;;; _@fadedwn_wait _T99
_@fadein_start pal_bg,bgpal_work,pal_sp,sppal_work,3,4
_@fadein_wait _T99
_@sprscrl_start 16,32,0,-1,1
_@bgscrl_start 0,-8,1
_sprscrl_lp:
cmpiw sprscrl_count,128
bne _sprscrl_lp
_@sprscrl_stop
_@wait 60*1,_T99
_@bgscrl_start 0,-7,1
_@wait 10,_T99
_@bgscrl_start 0,-6,1
_@wait 10,_T99
_@bgscrl_start 0,-5,1
_@wait 10,_T99
_@bgscrl_start 0,-4,1
_@wait 10,_T99
_@bgscrl_start 0,-3,1
_@wait 10,_T99
_@bgscrl_start 0,-2,1
_@wait 10,_T99
memcpy pal_bg,bgpal_work+$20,$20
inc pal_flg
_@bgscrl_start 0,-1,1
_@wait 10,_T99
_@bgscrl_start 0,1,1
_@wait 10,_T99
_lplp:
moviw x_tbl_ptr,x_tbl-2*(_Max_-1)
moviw y_tbl_ptr,y_tbl-2*(_Max_-1)
lda #85
sta counter
_change_x:
movmw src,x_tbl_ptr
moviw dst,xy
ldy #(2*_Max_)
jsr movsb
addmw rogo_tbl+(8*0)+2,xy+$12
addmw rogo_tbl+(8*1)+2,xy+$10
addmw rogo_tbl+(8*2)+2,xy+$0e
addmw rogo_tbl+(8*3)+2,xy+$0c
addmw rogo_tbl+(8*4)+2,xy+$0a
addmw rogo_tbl+(8*5)+2,xy+$08
addmw rogo_tbl+(8*6)+2,xy+$06
addmw rogo_tbl+(8*7)+2,xy+$04
addmw rogo_tbl+(8*8)+2,xy+$02
addmw rogo_tbl+(8*9)+2,xy+$00
_chenge_y:
movmw src,y_tbl_ptr
moviw dst,xy
ldy #(2*_Max_)
jsr movsb
submw rogo_tbl+(8*0),xy+$12
submw rogo_tbl+(8*1),xy+$10
submw rogo_tbl+(8*2),xy+$0e
submw rogo_tbl+(8*3),xy+$0c
submw rogo_tbl+(8*4),xy+$0a
submw rogo_tbl+(8*5),xy+$08
submw rogo_tbl+(8*6),xy+$06
submw rogo_tbl+(8*7),xy+$04
submw rogo_tbl+(8*8),xy+$02
submw rogo_tbl+(8*9),xy+$00
_next
lda counter
cmp #75
bcs _fore
cmp #55
jcs _back
cmp #35
bcs _fore
cmp #15
jcs _back
_fore:
memset sp_buf+128+64*2-(8*_Max_),zero,8*_Max_
moviw src,rogo_tbl
moviw dst,sp_buf
ldy #(8*_Max_)
jsr movsb
moviw rogo_tbl+(8*0)+6,$3181
moviw rogo_tbl+(8*1)+6,$3181
moviw rogo_tbl+(8*2)+6,$3181
moviw rogo_tbl+(8*3)+6,$3181
moviw rogo_tbl+(8*4)+6,$3181
moviw rogo_tbl+(8*5)+6,$3181
moviw rogo_tbl+(8*6)+6,$3181
moviw rogo_tbl+(8*7)+6,$3181
moviw rogo_tbl+(8*8)+6,$3181
moviw rogo_tbl+(8*9)+6,$3181
lda counter
_c1:
cmp #85
bne _c2
memset sp_buf+(8*1),zero,8*9
jmp _put_spr
_c2:
cmp #84
bne _c3
memset sp_buf+(8*2),zero,8*8
jmp _put_spr
_c3:
cmp #83
bne _c4
memset sp_buf+(8*3),zero,8*7
jmp _put_spr
_c4:
cmp #82
bne _c5
memset sp_buf+(8*4),zero,8*6
jmp _put_spr
_c5:
cmp #81
bne _c6
memset sp_buf+(8*5),zero,8*5
jmp _put_spr
_c6:
cmp #80
bne _c7
memset sp_buf+(8*6),zero,8*4
jmp _put_spr
_c7:
cmp #79
bne _c8
memset sp_buf+(8*7),zero,8*3
jmp _put_spr
_c8:
cmp #78
bne _c9
memset sp_buf+(8*8),zero,8*2
jmp _put_spr
_c9:
cmp #77
bne _c10
memset sp_buf+(8*9),zero,8*1
jmp _put_spr
_c10:
jmp _put_spr
_back:
memset sp_buf,zero,8*_Max_
moviw src,rogo_tbl
moviw dst,sp_buf+128+64*2-(8*_Max_)
ldy #(8*_Max_)
jsr movsb
moviw rogo_tbl+(8*0)+6,$3182
moviw rogo_tbl+(8*1)+6,$3182
moviw rogo_tbl+(8*2)+6,$3182
moviw rogo_tbl+(8*3)+6,$3182
moviw rogo_tbl+(8*4)+6,$3182
moviw rogo_tbl+(8*5)+6,$3182
moviw rogo_tbl+(8*6)+6,$3182
moviw rogo_tbl+(8*7)+6,$3182
moviw rogo_tbl+(8*8)+6,$3182
moviw rogo_tbl+(8*9)+6,$3182
_put_spr:
inc spr_flg
_@wait 2,_T99
incw x_tbl_ptr
incw x_tbl_ptr
incw y_tbl_ptr
incw y_tbl_ptr
dec counter
jne _change_x
_@wait 60*60,_T99
_@bgscrl_stop
;
; T99 ================================================================
;
call bgpal_clr
call sppal_clr
call sat_clr
call dspoff
call vsync
_T99:
call all_done
CDEXEC SELECTOR_BIN,$4000,1
;
counter db 0
xy ds 2*10
x_tbl_ptr dw x_tbl
ds 10*2
x_tbl dw 225,-25,-25,-25,-25,-25,-25,-25,-25,-25
dw 01, 02, 04, 08, 16, 16, 16, 16, 16, 32
dw 32, 16, 16, 16, 16, 16, 08, 04, 02, 01
dw -01,-02,-04,-08,-16,-16,-16,-16,-16,-32
dw -32,-16,-16,-16,-16,-16,-08,-04,-02,-01
dw 01, 02, 04, 08, 16, 16, 16, 16, 16, 32
dw 32, 16, 16, 16, 16, 16, 08, 04, 02, 01
dw -01,-02,-04,-08,-16,-16,-16,-16,-16,-16
dw -24,-24,-24,-24,-24, 00, 00, 00, 00, 00
y_tbl_ptr dw y_tbl
ds 2*10
y_tbl dw -97, 01, 01, 01, 02, 04, 08, 16, 32, 32
dw 08, 04, 04, 04, 04, 02, 02, 02, 02, 01
dw -01,-02,-02,-02,-02,-04,-04,-04,-04,-08
dw -08,-04,-04,-04,-04,-02,-02,-02,-02,-01
dw 01, 02, 02, 02, 02, 04, 04, 04, 04, 08
dw 08, 04, 04, 04, 04, 02, 02, 02, 02, 01
dw -01,-02,-02,-02,-02,-04,-04,-04,-04,-08
dw -08,-04,-04,-04,-04,-02,-02,-02,-02,-01
dw 00, 00, 00, 00, 00, 00, 00, 00, 00, 00
rogo_tbl dw 64+$40, $10,$0300,$3181 ;G
dw 64+$40, $10,$0320,$3181 ;O
dw 64+$40, $10,$0340,$3181 ;L
dw 64+$40, $10,$0360,$3181 ;D
dw 64+$40, $10,$0310,$3181 ;E
dw 64+$40, $10,$0330,$3181 ;N
dw 64+$40, $10,$0380,$3181 ;
dw 64+$40, $10,$03a0,$3181 ;A
dw 64+$40, $10,$03c0,$3181 ;X
dw 64+$40, $10,$0310,$3181 ;E
dummy ds 8
;
endChunk 7#
;
include macro.h
include biosw.h
include c62.h
;
; external functions =============================
;
extern entry
;
; zero seg work ==================================
;
seg zseg
;
; register work
;
public a0,a1,a2,a3,a4,a5,a6,a7
public d0,d1,d2,d3,d4,d5,d6,d7
a0 ds 2
a1 ds 2
a2 ds 2
a3 ds 2
a4 ds 2
a5 ds 2
a6 ds 2
a7 ds 2
d0 ds 2
d1 ds 2
d2 ds 2
d3 ds 2
d4 ds 2
d5 ds 2
d6 ds 2
d7 ds 2
;
;
;
public irq_cr
irq_cr ds 1
irq_sr ds 1
irq_ls ds 1
public pal_flg,spr_flg,anime_flg,done_flg
pal_flg ds 1
spr_flg ds 1
anime_flg ds 1
done_flg ds 1
done_count ds 1
pause_trg ds 1
;
; scroll work
;
public bgscrl_flg,bgscrl_x,bgscrl_y,bgscrl_wait,bgscrl_temp
bgscrl_flg ds 1
bgscrl_x ds 1
bgscrl_y ds 1
bgscrl_wait ds 1
bgscrl_temp ds 1
public sprscrl_flg,sprscrl_bank,sprscrl_bank_l
public sprscrl_x,sprscrl_y,sprscrl_wait,sprscrl_temp,sprscrl_count
sprscrl_flg ds 1
sprscrl_bank ds 1
sprscrl_bank_l ds 1
sprscrl_x ds 1
sprscrl_y ds 1
sprscrl_wait ds 1
sprscrl_temp ds 1
sprscrl_count ds 2
;
public palc_flg,palc_src_addr,palc_dst_addr,palc_start_addr,palc_end_addr
public palc_wait,palc_temp
palc_flg ds 1
palc_src_addr ds 2
palc_dst_addr ds 2
palc_start_addr ds 2
palc_end_addr ds 2
palc_wait ds 1
palc_temp ds 1
;
; fade in/out work
;
public fadeout_flg,fadeup_flg
public fadeout_addr1,fadeout_addr2,fadeout_palsize,fadeout_len
public fadeout_wait,fadeout_temp,fadeout_count
fadeout_flg ds 1
fadeup_flg ds 1
fadeout_addr1 ds 2
fadeout_addr2 ds 2
fadeout_palsize ds 2
fadeout_len ds 2
fadeout_wait ds 1
fadeout_temp ds 1
fadeout_count ds 1
public fadein_flg,fadedown_flg
public fadein_addr1,fadein_addr2,fadein_addr3,fadein_addr4
public fadein_palsize,fadein_len
public fadein_wait,fadein_temp,fadein_base,fadein_count
fadein_flg ds 1
fadedown_flg ds 1
fadein_addr1 ds 2
fadein_addr2 ds 2
fadein_addr3 ds 2
fadein_addr4 ds 2
fadein_palsize ds 2
fadein_len ds 2
fadein_wait ds 1
fadein_temp ds 1
fadein_base ds 1
fadein_count ds 1
pal_addr_0 ds 2
pal_addr_1 ds 2
pal_dat ds 2
pal_tmp ds 2
;
; animation work
;
public cab_bank,cab_ptr,pbank_ptr,sp_buf_ptr,animate_wait
public animate_x,animate_y,animate_spb,animate_mode,animate_bnum
cab_bank ds 1
cab_ptr ds 2
pbank_ptr ds 2
sp_buf_ptr ds 2
animate_wait ds 1
animate_x ds 2
animate_y ds 2
animate_spb ds 2
animate_mode ds 1
animate_bnum ds 1
;
;
public src,dst,src_i,dst_i,vsync_count,zero,efef,irq_counter
src ds 2
dst ds 2
src_i ds 2
dst_i ds 2
vsync_count ds 2
zero ds 2 ;$0000
efef ds 2 ;$ffff
irq_counter ds 2
;
public sp_x,sp_y,sp_addr,sp_c,sp_bg,bg_x,bg_y
sp_x ds 2
sp_y ds 2
sp_addr ds 2
sp_c ds 2
sp_bg ds 2
bg_x ds 1
bg_y ds 1
;
;
public regbox
regbox ds 1
;
; dseg work ======================================
;
seg dseg
public pal_bg,pal_sp,sp_buf
pal_bg ds 512
pal_sp ds 512
sp_buf ds 512
;
; cseg ===========================================
;
seg cseg
;
; COLD or SOFT start entry =======================
;
cold_start:
soft_reset:
sei
csh
ldx #$ff ;stack pointer
txs
clx
_move_lp:
lda $2000,x
sta $3f00,x
inx
bne _move_lp
; initialize 7up registers
jsr ini7up
jsr ex_dspoff ;BG and SPRITE display off
lda #1
jsr ex_scrsiz ;set screen size x=64 y=32
cla
ldx #32
ldy #28
jsr ex_scrmod ;set screen mode x=32 y=28
cla
jsr ex_dotmod ;set vram access dot size = 1
moviw sat_adr,$0f00 ;satbuf ;SATBUF = $0f00
; clear zseg
ldx #$dc
clp1:
dex
stz $2000,x ;$2000~$20db (20dc~21ff=reserved)
cpx #0
bne clp1
; clear dseg
stz A0 ;data area
lda #$23 ;$2300~$3eff (2200~22ff=reserved)
sta A0+1 ; (3f00~3fff=common area)
ldx #$1c
cla
clp2: cly
clp3: sta [a0],Y
iny
bne clp3
inc a0+1
dex
bne clp2
jsr vram_clr
jsr irq_set
stz irq_cr
stz crl_m
stz pal_flg
stz spr_flg
stz anime_flg
stz bgscrl_flg
stz palc_flg
stz bgscrl_x
stz bgscrl_y
stz animate_bnum
stzw bgx1
stzw bgy1
moviw sp_bg,$80
lda #$ff
sta efef
sta efef+1
jsr irq_on
jsr vsync
stz done_flg
lda #10
sta done_count
stz pause_trg
jmp entry
;--------------------------------------
; initialize 7up
;--------------------------------------
INI7UP:
MOVIW A0,INIDAT
LDY #0
INILP: LDA [A0],Y
INY
STA REGBOX
STA AR
LDA [A0],Y
INY
STA LOW7UP
LDA [A0],Y
INY
STA HI7UP
CPY #_INIDAT-INIDAT
BNE INILP
RTS
;
INIDAT:
DB CR ,$00,$00
;; DB RCR ,$5F,$00 ;割り込み
DB RCR ,$00,$00 ;割り込み
DB BXR ,$00,$00
DB BYR ,$00,$00
DB MWR ,$10,$00 ;64*32
DB HSR ,$02,$02
DB HDR ,$1F,$03 ;$1f,$04
DB VPR ,$02,$0F ;$04,$0e
DB VDR ,$EF,$00 ;$f0,$00
DB VCR ,$03,$00 ;$0c,$00
DB DCR ,$10,$00
DB DVSSR ,LOW($f00),HIGH($f00)
_INIDAT:
;
; set IRQ handler ================================
;
irq_set:
lda #$01
ldx #low (irq_handler)
ldy #high (irq_handler)
jsr ex_setvec
lda #%0000_0010
sta irq_m
rts
;
; IRQ handler ====================================
;
irq_handler:
pha
phx
phy
lda AR
sta irq_sr
and #$20 ;v blank interrupt ?
jeq IRQ_laster ;no then jump
jsr joyread
lda pause_trg
beq _irq_main
lda joy
bit #$01
jne irq_done
stz pause_trg
_irq_main:
lda vdtin_flg
jne irq_done2
setreg CR
lda crl_m
sta LOW7UP
setreg BXR
outmw bgx1
setreg BYR
outmw bgy1
stz irq_ls ;for laster interrupt
incw irq_counter
inc irq_cr
_bgscroll:
lda bgscrl_flg
beq _fadein
jsr bg_scrl
_fadein:
lda fadein_flg
beq _fadedown
jsr fade_in
_fadedown:
lda fadedown_flg
beq _fadeout
jsr fade_down
_fadeout:
lda fadeout_flg
beq _fadeup
jsr fade_out
_fadeup:
lda fadeup_flg
beq _palchange
jsr fade_up
_palchange:
lda palc_flg
beq _palette
jsr pal_change
_palette:
lda pal_flg
beq _animate
stz pal_sp
stz pal_sp+1
stzw CTA
tia pal_bg,CTW,512*2
stz pal_flg
_animate:
lda anime_flg ;animate flag
beq _sprscroll
jsr animate
_sprscroll:
lda sprscrl_flg ;sp scroll flag
beq _sprite
jsr spr_scrl
_sprite:
lda spr_flg ;sprite flag
beq irq_e
setreg MAWR
outmw sat_adr
setreg VWR
tia sp_buf,LOW7UP,512
setreg DVSSR
outmw sat_adr
stz spr_flg
irq_e:
stzw bgx2
stzw bgy2
lda done_flg
jne irq_done
_check_I_button:
;;; jsr joyread
lda joy
bit #$01
bne _wait_I_trg
bra _check_run_button
_wait_I_trg:
inc pause_trg
_check_run_button:
;;; lda joydata
lda joy
bit #$08
jeq _reset_done_count
dec done_count
jne irq_done
sta done_flg
_reset_done_count:
lda #10
sta done_count
jmp irq_done
public raster,odd_value,even_value,rcr_flg
raster dw 64
odd_value dw 256
even_value dw -256
rcr_flg db 0
irq_laster:
lda irq_sr
and #$04 ;laster interrupt ?
jeq irq_done ;no then jump
lda rcr_flg
jeq _normal_laster
_type1_laster:
cmpiw odd_value,0
jeq _rcr_done
_check_min:
cmpiw2 raster,64
bcs _check_max
bra _reset
_check_max:
cmpiw2 raster,64+32
jcc _rcr_exit
cmpiw2 raster,64*4+32
jcc _do_rcr
_reset:
moviw bgy2,0
moviw raster,64
setreg RCR
outmw raster
subiw odd_value,8
addiw even_value,8
jmp irq_laster_e
_do_rcr:
lda raster
bit #1
beq _set_even
_set_odd:
movmw bgx2,odd_value
bra _rcr_exit
_set_even:
movmw bgx2,even_value
bra _rcr_exit
_rcr_done:
stzw bgx2
stzw bgy2
stzw raster
setreg RCR
outiw raster
stz rcr_flg
bra irq_laster_e
_rcr_exit:
setreg BXR
outmw bgx2
setreg BYR
outmw bgy2
incw raster
setreg RCR
outmw raster
incw bgy2
bra irq_laster_e
_normal_laster:
lda irq_ls
jne irq_e
setreg BXR
outmw bgx1
setreg BYR
outmw bgy1
irq_laster_e:
inc irq_ls ;increment flag
irq_done:
lda regbox
sta AR
irq_done2:
ply
plx
pla
rti
;--------------------------------------
; read joy card (5 players)
;--------------------------------------
public joyread
JOYREAD:
CLY
LDA #%0000_0001 ; clr low , sel high
STA JOYIO
LDA #%0000_0011 ; clr high
STA JOYIO
JOY_PAD_LOOP1: ; pad read ( 5 times )
LDA #%0000_0001 ; sel high
STA JOYIO
PHA ; 1.24us delay
PLA ;
NOP ;
;;; LDA JOYDATA,Y
LDA JOY,Y
STA JOYOLD,Y
LDA JOYIO
ASL A
ASL A
ASL A
ASL A
;;; STA JOYDATA,Y
STA JOY,Y
STZ JOYIO
PHA ; 1.24us delay
PLA ;
NOP ;
LDA JOYIO
AND #%0000_1111
;;; ORA JOYDATA,Y
ORA JOY,Y
EOR #$FF
;;; STA JOYDATA,Y
STA JOY,Y
EOR JOYOLD,Y
;;; AND JOYDATA,Y
AND JOY,Y
STA JOYTRG,Y
INY
CPY #5
BCC JOY_PAD_LOOP1
CLY ; soft reset check
JOY_PAD_LOOP2:
LDA JOYENA
AND JOY_PAD_TABLE,Y
BEQ JOY_PAD_rts
LDA JOYTRG,Y
CMP #JOYSELECT
BNE JOY_PAD_rts
;;; LDA JOYDATA,Y
LDA JOY,Y
CMP #JOYSELECT+JOYSTART
BNE JOY_PAD_rts
jsr cd_boot
JOY_PAD_rts:
INY
CPY #5
BCC JOY_PAD_LOOP2
RTS
JOY_PAD_TABLE:
DB 1,2,4,8,16
;
; TIMER INTERRUPT handler ========================
;
timer_handler:
phy
phx
pha
sta IRQREG
cli
bsr c62_sound
pla
plx
ply
rti
;
; PSG handler ====================================
;
public c62_sound
c62_sound:
rts
public set_music
set_music:
rts
;
; clear VRAM ($0000 ~ $7fff) =====================
;
public vram_clr
vram_clr:
setreg MAWR
outiw $0000
setreg VWR
moviw d0,$8000
_vramclr_lp:
stz LOW7UP
stz HI7UP
decw d0
cmpiw d0,0
bne _vramclr_lp
rts
;
; clear SP PALETTE ===============================
;
public sppal_clr
sppal_clr:
memset pal_sp,zero,512
inc pal_flg
jsr vsync
rts
;
; clear BG PALETTE ===============================
;
public bgpal_clr
bgpal_clr:
memset pal_bg,zero,512
inc pal_flg
jsr vsync
rts
;
; clear SAT ======================================
;
public sat_clr
sat_clr:
memset sp_buf,zero,512
setreg MAWR
outmw sat_adr
setreg VWR
tia sp_buf,LOW7UP,512
setreg DVSSR
outmw sat_adr
rts
;
; trans memory to vram ===========================
;
; public mem_to_vram
;mem_to_vram:
; ldy #16
;_lplp1:
; phy
; clx
;_lplp2:
; phx
; setreg MAWR
; outmw vram_adr
; setreg VWR
; lda [mem_adr]
; sta LOW7UP
; incw mem_adr
; lda [mem_adr]
; sta HI7UP
; incw mem_adr
; incw vram_adr
; plx
; dex
; bne _lplp2
; ply
; dey
; bne _lplp1
; rts
;
; bg scroll ======================================
; in. bgscrl_x=x
; bgscrl_y=y
; bgscrl_wait=wait time
;
public bg_scrl
bg_scrl:
lda bgscrl_wait
beq _bgscrl_0
dec bgscrl_temp
bne _bgscrl_1
_bgscrl_0:
addmb bgx1,bgscrl_x
addmb bgy1,bgscrl_y
mov bgscrl_temp,bgscrl_wait
_bgscrl_1:
setreg BXR
outmw bgx1
setreg BYR
outmw bgy1
rts
;
; sprite scroll ==================================
; in. sprscrl_x=x
; sprscrl_y=y
; sprscrl_wait=wait time
;
spr_bank_ptr ds 2
spr_bank ds 2
public spr_scrl
spr_scrl:
lda sprscrl_wait
beq _sprscrl_0
dec sprscrl_temp
jne _sprscrl_1
_sprscrl_0:
mov sprscrl_temp,sprscrl_wait
moviw spr_bank_ptr,sp_buf
lda sprscrl_bank
asl a
asl a
asl a
sta spr_bank
stz spr_bank+1
addmw spr_bank_ptr,spr_bank
ldx sprscrl_bank_l
_sprscrl_lp:
phx
movdati L0950_ptr,spr_bank_ptr,4
addmb y_offset,sprscrl_y
addmb x_offset,sprscrl_x
movdati spr_bank_ptr,L0950_ptr,4
addiw spr_bank_ptr,8
plx
dex
jne _sprscrl_lp
incw sprscrl_count
inc spr_flg
;; setreg MAWR
;; outmw sat_adr
;; setreg VWR
;; tia sp_buf,LOW7UP,512
;; setreg DVSSR
;; outmw sat_adr
_sprscrl_1:
rts
;
; palette change =================================
; in. palc_wait=wait time
; palc_src_addr=source palc ptr
; palc_start_addr=start palc addr
; palc_end_addr=end palc addr
; palc_dst_addr=destination palc addr
;
public pal_change
pal_change:
lda palc_wait
beq _palc_0
dec palc_temp
bne _palc_2
cmpmw2 palc_start_addr,palc_end_addr
;; jge _palc_1
bcs _palc_1
_palc_0:
mov palc_temp,palc_wait
addiw palc_src_addr,$20
cmpmw palc_src_addr,palc_end_addr
beq _palc_2
cmpmw2 palc_src_addr,palc_end_addr
;; jl _palc_2
bcc _palc_2
movmw palc_src_addr,palc_start_addr
bra _palc_2
_palc_1:
mov palc_temp,palc_wait
subiw palc_src_addr,$20
cmpmw2 palc_src_addr,palc_end_addr
;; jge _palc_2
bcs _palc_2
movmw palc_src_addr,palc_start_addr
_palc_2:
movmw src_i,palc_src_addr
movmw dst_i,palc_dst_addr
ldy #$20
jsr movsb_i
inc pal_flg
rts
;
; fade out =======================================
; in. fadeout_addr1=palette addr
; fadeout_wait=wait time
; fadeout_palsize=pallette length
;
pal_incval dw 0
public fade_out
fade_out:
cmpiw fadeout_len,0
bne _fadeout_start
lda fadeout_wait
beq _fadeout_lp0
dec fadeout_temp
jne _fadeout_exit
_fadeout_lp0:
mov fadeout_temp,fadeout_wait
movmw fadeout_len,fadeout_palsize
stzw pal_incval
_fadeout_start:
movmw pal_addr_0,fadeout_addr1
addmw pal_addr_0,pal_incval
movmw pal_addr_1,fadeout_addr1
addmw pal_addr_1,pal_incval
jsr fadeout_s
movmw pal_addr_0,fadeout_addr2
addmw pal_addr_0,pal_incval
movmw pal_addr_1,fadeout_addr2
addmw pal_addr_1,pal_incval
jsr fadeout_s
inc pal_flg
addiw pal_incval,32
decw fadeout_len
cmpiw fadeout_len,0
bne _fadeout_exit
stzw pal_incval
dec fadeout_count
bne _fadeout_exit
stz fadeout_flg
mov fadeout_count,#$07
_fadeout_exit:
rts
fadeout_s:
ldx #16
_fadeout_lp1:
phx
mov pal_tmp+0,[pal_addr_0]
incw pal_addr_0
mov pal_tmp+1,[pal_addr_0]
incw pal_addr_0
_out_B:
lda pal_tmp+0 ;Blue
and #%0000_0111
beq _set_out_B
dec a
_set_out_B:
sta pal_dat+0
_out_R:
lda pal_tmp+0 ;Red
lsr a
lsr a
lsr a
and #%0000_0111
beq _set_out_R
dec a
_set_out_R:
asl a
asl a
asl a
ora pal_dat+0
sta pal_dat+0
_out_G:
lda pal_tmp+1 ;Green
ror a
lda pal_tmp+0
ror a
lsr a
lsr a
lsr a
lsr a
lsr a
and #%0000_0111
beq _set_out_G
dec a
_set_out_G:
clc
ror a
ror a
ror a
tax
rol a
and #%0000_0001
sta pal_dat+1
txa
ora pal_dat+0
sta pal_dat+0
_restore_fadeout_data:
mov [pal_addr_1],pal_dat+0
incw pal_addr_1
mov [pal_addr_1],pal_dat+1
incw pal_addr_1
plx
dex
jne _fadeout_lp1
rts
;
; fade up ========================================
; in. fadeout_addr1=palette addr
; fadeout_wait=wait time
; fadeout_palsize=pallette length
;
public fade_up
fade_up:
cmpiw fadeout_len,0
bne _fadeup_start
lda fadeout_wait
beq _fadeup_lp0
dec fadeout_temp
jne _fadeup_exit
_fadeup_lp0:
mov fadeout_temp,fadeout_wait
movmw fadeout_len,fadeout_palsize
stzw pal_incval
_fadeup_start:
movmw pal_addr_0,fadeout_addr1
addmw pal_addr_0,pal_incval
movmw pal_addr_1,fadeout_addr1
addmw pal_addr_1,pal_incval
jsr fadeup_s
movmw pal_addr_0,fadeout_addr2
addmw pal_addr_0,pal_incval
movmw pal_addr_1,fadeout_addr2
addmw pal_addr_1,pal_incval
jsr fadeup_s
inc pal_flg
addiw pal_incval,32
decw fadeout_len
cmpiw fadeout_len,0
bne _fadeup_exit
stzw pal_incval
dec fadeout_count
bne _fadeup_exit
stz fadeup_flg
mov fadeout_count,#$07
_fadeup_exit:
rts
fadeup_s:
ldx #16
_fadeup_lp1:
phx
mov pal_tmp+0,[pal_addr_0]
incw pal_addr_0
mov pal_tmp+1,[pal_addr_0]
incw pal_addr_0
_up_B:
lda pal_tmp+0 ;Blue
and #%0000_0111
cmp #%0000_0111
beq _set_up_B
inc a
_set_up_B:
sta pal_dat+0
_up_R:
lda pal_tmp+0 ;Red
lsr a
lsr a
lsr a
and #%0000_0111
cmp #%0000_0111
beq _set_up_R
inc a
_set_up_R:
asl a
asl a
asl a
ora pal_dat+0
sta pal_dat+0
_up_G:
lda pal_tmp+1 ;Green
ror a
lda pal_tmp+0
ror a
lsr a
lsr a
lsr a
lsr a
lsr a
cmp #%0000_0111
beq _set_up_G
inc a
clc
_set_up_G:
ror a
ror a
ror a
tax
rol a
and #%0000_0001
sta pal_dat+1
txa
ora pal_dat+0
sta pal_dat+0
_restore_fadeup_data:
mov [pal_addr_1],pal_dat+0
incw pal_addr_1
mov [pal_addr_1],pal_dat+1
incw pal_addr_1
plx
dex
jne _fadeup_lp1
rts
;
; fade in ========================================
; in. fadein_addr1=palette addr
; fadein_addr2=source addr
; fadein_wait=wait time
; fadein_palsize=pallette length
;
public fade_in
fade_in:
cmpiw fadein_len,0
bne _fadein_start
lda fadein_wait
beq _fadein_lp0
dec fadein_temp
jne _fadein_exit
_fadein_lp0:
mov fadein_temp,fadein_wait
movmw fadein_len,fadein_palsize
stzw pal_incval
_fadein_start:
movmw pal_addr_0,fadein_addr2
addmw pal_addr_0,pal_incval
movmw pal_addr_1,fadein_addr1
addmw pal_addr_1,pal_incval
jsr fadein_s
movmw pal_addr_0,fadein_addr4
addmw pal_addr_0,pal_incval
movmw pal_addr_1,fadein_addr3
addmw pal_addr_1,pal_incval
jsr fadein_s
inc pal_flg
addiw pal_incval,32
decw fadein_len
cmpiw fadein_len,0
bne _fadein_exit
stzw pal_incval
dec fadein_base
dec fadein_count
bne _fadein_exit
stz fadein_flg
mov fadein_count,#$08
mov fadein_base,#$07
_fadein_exit:
rts
fadein_s:
ldx #16
_fadein_lp1:
phx
stzw pal_dat
mov pal_tmp+0,[pal_addr_0]
incw pal_addr_0
mov pal_tmp+1,[pal_addr_0]
incw pal_addr_0
_in_B:
lda pal_tmp+0 ;Blue
and #%0000_0111
beq _set_in_B
cmp fadein_base
;; jl _set_in_B
bcc _set_in_B
sub fadein_base
sta pal_dat+0
_set_in_B:
_in_R:
lda pal_tmp+0 ;Red
lsr a
lsr a
lsr a
and #%0000_0111
beq _set_in_R
cmp fadein_base
;; jl _set_in_R
bcc _set_in_R
sub fadein_base
asl a
asl a
asl a
ora pal_dat+0
sta pal_dat+0
_set_in_R:
_in_G:
lda pal_tmp+1 ;Green
ror a
lda pal_tmp+0
ror a
lsr a
lsr a
lsr a
lsr a
lsr a
and #%0000_0111
beq _set_in_G
cmp fadein_base
;; jl _set_in_G
bcc _set_in_G
sub fadein_base
clc
ror a
ror a
ror a
tax
rol a
and #%0000_0001
sta pal_dat+1
txa
ora pal_dat+0
sta pal_dat+0
_set_in_G:
_restore_fadein_data:
mov [pal_addr_1],pal_dat+0
incw pal_addr_1
mov [pal_addr_1],pal_dat+1
incw pal_addr_1
plx
dex
jne _fadein_lp1
rts
;
; fade down ======================================
; in. fadein_addr1=palette addr
; fadein_addr2=source addr
; fadein_wait=wait time
; fadein_palsize=pallette length
;
public fade_down
fade_down:
cmpiw fadein_len,0
bne _fadedown_start
lda fadein_wait
beq _fadedown_lp0
dec fadein_temp
jne _fadedown_exit
_fadedown_lp0:
mov fadein_temp,fadein_wait
movmw fadein_len,fadein_palsize
stzw pal_incval
_fadedown_start:
movmw pal_addr_0,fadein_addr2
addmw pal_addr_0,pal_incval
movmw pal_addr_1,fadein_addr1
addmw pal_addr_1,pal_incval
jsr fadedown_s
movmw pal_addr_0,fadein_addr4
addmw pal_addr_0,pal_incval
movmw pal_addr_1,fadein_addr3
addmw pal_addr_1,pal_incval
jsr fadedown_s
inc pal_flg
addiw pal_incval,32
decw fadein_len
cmpiw fadein_len,0
bne _fadedown_exit
stzw pal_incval
dec fadein_base
dec fadein_count
bne _fadedown_exit
stz fadedown_flg
mov fadein_count,#$08
mov fadein_base,#$07
_fadedown_exit:
rts
fadedown_s:
ldx #16
_fadedown_lp1:
phx
stzw pal_dat
mov pal_tmp+0,[pal_addr_0]
incw pal_addr_0
mov pal_tmp+1,[pal_addr_0]
incw pal_addr_0
_down_B:
lda pal_tmp+0 ;Blue
and #%0000_0111
cmp fadein_base
;; jge _set_down_B
bcs _set_down_B
lda fadein_base
_set_down_B:
sta pal_dat+0
_down_R:
lda pal_tmp+0 ;Red
lsr a
lsr a
lsr a
and #%0000_0111
cmp fadein_base
;; jge _set_down_R
bcs _set_down_R
lda fadein_base
_set_down_R:
asl a
asl a
asl a
ora pal_dat+0
sta pal_dat+0
_down_G:
lda pal_tmp+1 ;Green
ror a
lda pal_tmp+0
ror a
lsr a
lsr a
lsr a
lsr a
lsr a
and #%0000_0111
cmp fadein_base
;; jge _set_down_G
bcs _set_down_G
lda fadein_base
_set_down_G:
clc
ror a
ror a
ror a
tax
rol a
and #%0000_0001
sta pal_dat+1
txa
ora pal_dat+0
sta pal_dat+0
_restore_fadedown_data:
mov [pal_addr_1],pal_dat+0
incw pal_addr_1
mov [pal_addr_1],pal_dat+1
incw pal_addr_1
plx
dex
jne _fadedown_lp1
rts
;
; display SP bank ================================
; in. Areg = bank no. (vram)
;
public sp_bank_disp
sp_bank_disp:
pha
moviw src,sp_bank_dum
moviw dst,sp_bank_tbl
ldy #64
jsr movsb
pla
sta d0
stz d0+1
ldx #7
_calc_addr:
shlw d0
dex
bne _calc_addr
moviw d1,sp_bank_tbl+4
ldx #8
_set_addr:
moviw src,d0
movmw dst,d1
ldy #2
jsr movsb
addiw d1,8
addiw d0,$10
dex
bne _set_addr
addmw sp_bank_tbl+$00,sp_y
addmw sp_bank_tbl+$08,sp_y
addmw sp_bank_tbl+$10,sp_y
addmw sp_bank_tbl+$18,sp_y
addmw sp_bank_tbl+$20,sp_y
addmw sp_bank_tbl+$28,sp_y
addmw sp_bank_tbl+$30,sp_y
addmw sp_bank_tbl+$38,sp_y
addmw sp_bank_tbl+$00+2,sp_x
addmw sp_bank_tbl+$08+2,sp_x
addmw sp_bank_tbl+$10+2,sp_x
addmw sp_bank_tbl+$18+2,sp_x
addmw sp_bank_tbl+$20+2,sp_x
addmw sp_bank_tbl+$28+2,sp_x
addmw sp_bank_tbl+$30+2,sp_x
addmw sp_bank_tbl+$38+2,sp_x
addmw sp_bank_tbl+$00+6,sp_c
addmw sp_bank_tbl+$08+6,sp_c
addmw sp_bank_tbl+$10+6,sp_c
addmw sp_bank_tbl+$18+6,sp_c
addmw sp_bank_tbl+$20+6,sp_c
addmw sp_bank_tbl+$28+6,sp_c
addmw sp_bank_tbl+$30+6,sp_c
addmw sp_bank_tbl+$38+6,sp_c
addmw sp_bank_tbl+$00+6,sp_bg
addmw sp_bank_tbl+$08+6,sp_bg
addmw sp_bank_tbl+$10+6,sp_bg
addmw sp_bank_tbl+$18+6,sp_bg
addmw sp_bank_tbl+$20+6,sp_bg
addmw sp_bank_tbl+$28+6,sp_bg
addmw sp_bank_tbl+$30+6,sp_bg
addmw sp_bank_tbl+$38+6,sp_bg
moviw src,sp_bank_tbl
moviw dst,sp_buf
addmw dst,sp_addr
ldy #64
jsr movsb
;; inc spr_flg
setreg MAWR
outmw sat_adr
setreg VWR
tia sp_buf,LOW7UP,512
setreg DVSSR
outmw sat_adr
rts
sp_bank_tbl dw 0+$40, 0+$20,$0080,$3100 ;$1000
dw 64+$40, 0+$20,$0090,$3100 ;$1200
dw 0+$40,32+$20,$00a0,$3100 ;$1400
dw 64+$40,32+$20,$00b0,$3100 ;$1600
dw 0+$40,64+$20,$00c0,$3100 ;$1800
dw 64+$40,64+$20,$00d0,$3100 ;$1a00
dw 0+$40,96+$20,$00e0,$3100 ;$1c00
dw 64+$40,96+$20,$00f0,$3100 ;$1e00
sp_bank_dum dw 0+$40, 0+$20,$0080,$3100 ;$1000
dw 64+$40, 0+$20,$0090,$3100 ;$1200
dw 0+$40,32+$20,$00a0,$3100 ;$1400
dw 64+$40,32+$20,$00b0,$3100 ;$1600
dw 0+$40,64+$20,$00c0,$3100 ;$1800
dw 64+$40,64+$20,$00d0,$3100 ;$1a00
dw 0+$40,96+$20,$00e0,$3100 ;$1c00
dw 64+$40,96+$20,$00f0,$3100 ;$1e00
;
; display BG bank ================================
; in. Areg = bank no. (vram)
;
public bg_bank_disp
bg_bank_disp:
sta d0+1
stz d0+0
moviw a0,$0000
_set_bg_y:
ldx bg_y
beq _set_bg_x
_set_bg_y_lp:
addiw a0,$40
dex
bne _set_bg_y_lp
_set_bg_x:
ldx bg_x
beq _map
_set_bg_x_lp:
addiw a0,$1
dex
bne _set_bg_x_lp
_map:
ldy #$10
jsr vsync
map_y:
setreg MAWR
outmw a0
setreg VWR
ldx #$10
map_x:
outmw d0
incw d0
dex
bne map_x
addiw a0,$0040
dey
bne map_y
rts
;
; display PE bank ================================
; in. Areg = bank no. (vram)
;
public pe_disp
pe_disp:
sta d0+1
stz d0+0
moviw a0,$0000
ldy #$20
jsr vsync
pe_y:
setreg MAWR
outmw a0
setreg VWR
ldx #$20
pe_x:
outmw d0
incw d0
dex
bne pe_x
addiw a0,$0040
dey
bne pe_y
rts
;
; animate (with animation data)===================
; in. cab_bank = bank no. (memory)
;
zero_buf ds 128
zero_buf_ptr dw zero_buf
L0000_ptr dw _0000
L0950_ptr dw _0950
_0000:
pbank_num ds 1
wait_time ds 1
x_vector ds 1
y_vector ds 1
_0950:
y_offset ds 2
x_offset ds 2
pc_num ds 2
attr_code ds 2
public animate
animate:
tma4
pha
lda cab_bank
sec
sbc #$38
clc
adc max_mapping
tam4
lda animate_wait
beq _animate_start
dec animate_wait
jne animate_exit
jmp _animate_lp
_animate_start:
moviw cab_ptr,$8000
_animate_lp:
movdati L0000_ptr,cab_ptr,4
lda pbank_num
ora wait_time
jeq animate_done
addiw cab_ptr,4
moviw sp_buf_ptr,sp_buf
lda animate_bnum
beq _fill_blank
movdati sp_buf_ptr,zero_buf_ptr,16*8
_fill_blank:
addmw sp_buf_ptr,animate_spb
movdati sp_buf_ptr,zero_buf_ptr,16*8
addiw sp_buf_ptr,128-8
moviw pbank_ptr,$8000
addiw pbank_ptr,($950-8)
lda pbank_num
cmp #$00
beq _one_sprite
ldx pbank_num
_srch_pbank:
addiw pbank_ptr,8
movdati L0950_ptr,pbank_ptr,2
cmpiw y_offset,$ffff
bne _srch_pbank
dex
bne _srch_pbank
_one_sprite:
addiw pbank_ptr,8
movdati L0950_ptr,pbank_ptr,8
cmpiw y_offset,$ffff
jeq _next_sprite
addiw y_offset,64+$40 ;+$30
addmb y_offset,y_vector
addmw y_offset,animate_y
addiw x_offset,64+$20 ;+$20
addmb x_offset,x_vector
addmw x_offset,animate_x
addiw pc_num,$80
;- oraiw attr_code,$80
oramw attr_code,sp_bg
movdati sp_buf_ptr,L0950_ptr,8
subiw sp_buf_ptr,8
jmp _one_sprite
_next_sprite:
inc spr_flg
mov animate_wait,wait_time
jmp animate_exit
animate_done:
stz spr_flg
stz animate_wait
lda animate_mode
bne animate_exit
stz anime_flg
animate_exit:
pla
tam4
rts
;
; movsb ==========================================
; in. Yreg = Byte Count
; src = Soure Pointer
; dst = Destination Pointer
;
public movsb
movsb:
lda [src]
sta [dst]
incw src
incw dst
dey
bne movsb
rts
;
; movsb (use in interrupt routine) ===============
; in. Yreg = Byte Count
; src = Soure Pointer
; dst = Destination Pointer
;
public movsb_i
movsb_i:
lda [src_i] ;Block Trans 8 Byte
sta [dst_i]
incw src_i
incw dst_i
dey
bne movsb_i
rts
;
; all done procs =================================
;
extern stop_audio
public all_done
all_done:
stz pal_flg
stz palc_flg
stz fadein_flg
stz fadeout_flg
stz fadeup_flg
stz fadedown_flg
stz done_flg
lda #$0c
jsr cd_fade
moviw fadeout_addr1,pal_bg
moviw fadeout_addr2,pal_sp
moviw fadeout_palsize,8
moviw fadeout_len,0
mov fadeout_wait,#1
mov fadeout_temp,#1
mov fadeout_count,#7
inc fadeout_flg
__fo_end_lp:
lda fadeout_flg
bne __fo_end_lp
stz spr_flg
stz anime_flg
stz bgscrl_flg
stz sprscrl_flg
;; jsr cd_pause
;; jsr stop_audio
rts
;
; vsync wait =====================================
;
public vsync
vsync:
lda irq_cr
_vsync_lp:
cmp irq_cr
beq _vsync_lp
rts
;
; key(joypad) wait ===============================
;
public joy_wait
joy_wait:
_joy0:
lda joytrg
bne _joy0
_joy1:
lda joytrg
beq _joy1
rts
;
; WINDOW mode on/off =============================
;
public win_on
public win_flat
public win_off
win_on:
setreg HSR
outiw $0a02
setreg HDR
outiw $040f
; setreg HSR
; outiw $0202
; setreg HDR
; outiw $041f
setreg VPR
outiw $4602
setreg VDR
outiw $007f
rts
win_flat:
; setreg HSR
; outiw $0a02
; setreg HDR
; outiw $040f
setreg HSR
outiw $0202
setreg HDR
outiw $041f
setreg VPR
outiw $4602
setreg VDR
outiw $007f
rts
win_off:
setreg HSR
outiw $0202
setreg HDR
outiw $041f
setreg VPR
outiw $0f02
setreg VDR
outiw $00ef
rts
;
; IRQ on/off =====================================
;
public irq_on
public irq_off
irq_on:
setreg CR
lda crl_m
;; ora #$08 ;%0000_1000
ora #$0c ;%0000_1000
sta crl_m
sta LOW7UP
stz IRQDIS
cli
rts
irq_off:
sei
lda #$03
sta IRQDIS
setreg CR
lda crl_m
;; and #$f7 ;%1111_0111
and #$f3 ;%1111_0111
sta crl_m
sta LOW7UP
rts
;
; RCR on/off =====================================
;
public rcr_on
public rcr_off
rcr_on:
sei
setreg CR
lda crl_m
ora #$04 ;%0000_0100
sta crl_m
sta LOW7UP
cli
rts
rcr_off:
sei
setreg CR
lda crl_m
and #$fb ;%1111_1011
sta crl_m
sta LOW7UP
cli
rts
;
; TIMER on/off ===================================
;
; public timer_on
; public timer_off
;timer_on:
; lda timer
; sta timeriport
; lda #1
; sta timerport
; rts
;timer_off:
; stz timerport
; rts
;
; BG & SP on/off =================================
;
public dspon
public dspoff
dspon:
lda crl_m
ora #$c0
sta crl_m
jsr vsync
rts
dspoff:
lda crl_m
and #$3f
sta crl_m
jsr vsync
rts
;
; BG on/off ======================================
;
public bgon
public bgoff
bgon:
lda crl_m
ora #$80
sta crl_m
rts
bgoff:
lda crl_m
and #$7f
sta crl_m
rts
;
; SP on/off ======================================
;
public spron
public sproff
spron:
lda crl_m
ora #$40
sta crl_m
rts
sproff:
lda crl_m
and #$bf
sta crl_m
rts
public ad_read2
reg MACRO regster
lda #regster
sta reg_box
st0 #regster
ENDM
MAX_RATE equ $10 ;adpcm max divpt + 1
P_ADL equ $1808 ;( /W) address ratch low
P_ADH equ $1809 ;(W/O) address ratch high
P_ADSTAT equ $180c ;(R/O) ADPCM status in
P_ADCTL equ $180d ;(R/W) ADPCM play control
P_DIVPT equ $180e ;(R/W) ADPCM sampling late set
P_DRAM equ $180a ;(R/W) ADPCM buff <--> CPU data communication
P_INTCTL equ $1802 ;(R/W) ACK On/Off & INT mode set
P_INTMON equ $1803 ;(R/O) interapt monitor
;====================================================================
seg dseg
mprbox: ds 1
tmatamwk: ds 3
;====================================================================
seg cseg
;====================================================================
; AD_READ2 read data from ADPCM buff to memory
;
; in _CL: ADPCM BUFF ADR L
; _CH: ADPCM BUFF ADR H
; _DH: DESTINATION TYPE
; 00:LOCAL FF:VRAM ELSE:MPR NO.(2-6)
; _BL: ADR L ADR L BANK NO.
; _BH: ADR H ADR H NO USE
; _AL: BYTE LENGTH L
; _AH: BYTE LENGTH H
;
; out AREG: $00 OK
; ELSE ERROR
;
ad_read2:
jsr ver_chk
jne ad_read ;(BIOS)
jsr _adstat ;ADPCM PLAYING ?
bne ad_read2
lda _cl
sta P_ADL
lda _ch
sta P_ADH
jsr strdcnt
jsr read_one ;trans trigger
lda _dh ;dest.adr type
beq ardtomem ;to local
cmp #$ff
beq ardtovrm ;to vram
jmp ardtompr ;with mpr
;--------------------------------------------------------------------
; adpcm read to local memory (_DH = 0)
;
ardtomem:
jsr read_one
sta [_bx]
inc _bl
bne ardtm1
inc _bh
ardtm1: lda _al
bne ardtm2
dec _ah
ardtm2: dec _al
lda _al
ora _ah
bne ardtomem
cla
ardtome: rts
;--------------------------------------------------------------------
; adpcm read to 7up memory (_DH = $ff)
;
ardtovrm:
lda #1
sta vdtin_flg
REG MAWR ;set 7up vram target adr.
lda _bl
sta LOW7UP
lda _bh
sta HI7UP
REG VWR
lda #2 ;L7UP
sta _bl
stz _bh
ardtv0: jsr read_one
sta [_bx]
lda _bl
eor #1
sta _bl
lda _al
bne ardtv1
dec _ah
ardtv1: dec _al
lda _al
ora _ah
bne ardtv0
stz vdtin_flg
cla
ardtve: rts
;--------------------------------------------------------------------
; adpcm read with mpr (_DH = 2...6)
;
ardtompr:
cmp #7 ;mpr => (2...6)
bmi ardtp
lda #$22 ;invalid parameter
rts
ardtp: tax
lda #1
ardtp0: asl a
dex
bne ardtp0
sta tmatamwk+1
lda #$43 ;tma
sta tmatamwk
lda #$60 ;rts
sta tmatamwk+2
jsr tmatamwk ;<tma> get current bank No.
sta mprbox
lda _bl ;target bank no.
sta _dl ;push
ardtoplop: lda _dh ;mpr * $2000
asl a
asl a
asl a
asl a
asl a
sta _bh ;destination address high
stz _bl ;destination address high
lda #$53 ;tam
sta tmatamwk
lda _dl ;target bank
jsr tmatamwk ;<tam> set mpr target bank
ldx #32
cly
ardtp1: jsr read_one
sta [_bx]
inc _bl ;increment dest.adr
bne ardtp2
inc _bh
ardtp2: lda _al
bne ardtpb
dec _ah
ardtpb: dec _al
lda _al
ora _ah
beq ardtope
ardtp3: dey
bne ardtp1
dex
bne ardtp1
inc _dl ;increment bank No.
bra ardtoplop
ardtope: lda #$53 ;tam
sta tmatamwk
lda mprbox
jsr tmatamwk ;<tam> set mpr original bank
cla
rts
;====================================================================
; READ_ONE byte read from adpcm
; out = acc
;
read_one:
lda P_ADSTAT
bmi read_one
lda P_DRAM
rts
;====================================================================
; VER_CHK check BIOS version
; out Z = 1 ok(1.00)
;
ver_chk:
jsr ex_getver
dex ;cpx #$01
bne ver_chk_exit
tya ;cpy #$00
ver_chk_exit:
rts
;====================================================================
; _ADSTAT get status of ADPCM
;
; in none
;
; out areg: $00 ADPCM NOT BUSY (END OR NOT PLAY)
; ELSE ADPCM BUSY
; xreg: intmonitor
; $01 AD END
; $04 AD HALF
;
_adstat:
lda P_ADSTAT ;19880910
and #%0000_0001 ;AD_END
bne _adstatx ;19880910
lda P_INTMON
and #%0000_0100 ;INT_A
_adstatx: tax
lda P_ADCTL
and #%0010_0000 ;ADPCM.ON
bne _adstate
lda P_ADSTAT
and #%0000_1000 ;ADPCM.BSY
_adstate: rts
;====================================================================
; STRDCNT set adpcm read counter
; P_ADL,P_ADH must be set before call me
;
strdcnt:
lda #%0000_1000 ;READ LD ON
tsb P_ADCTL
lda P_DRAM ;DUMMY READ for ADR LATCH
lda #5
dec a
bne *-1
lda #%0000_1000 ;READ LD OFF
trb P_ADCTL
rts
endChunk 8#
;
; TYRIS FLARE (Opening)
;
include macro.h
include visual.h
include biosw.h
include c62.h
include uty.h
include inf_b.h
player equ $2000
stage equ $2001
player_s equ $3f00
stage_s equ $3f01
mode equ $3ffe
;
public entry
;
seg dseg
sppal_work ds 2048+$100
bgpal_work ds 2048+$100
subcode_buff ds 10
seg cseg
entry:
jmp startup
data1:
data TOC1_PCB,bgpal_work,1,LOCAL
data TOC1_PBB,$1000,4*4,VRAM
data T2_CCB,bgpal_work+$20,1,LOCAL
data T2_CBB,$5000,4,VRAM
data C03A_CCB,bgpal_work+$40,1,LOCAL
data C03A_CBB,$6000,4*1,VRAM
;MAPREG 4,$3a
data C03AN_CAB,$8000,4*1,LOCAL
;MAPREG 5,$3b
data C03B_CCB,sppal_work+$40,1,LOCAL
data C03B_CSB,$a000,4*1,LOCAL
data C04_CCB,bgpal_work+$60,1,LOCAL
data C04_CBB,$7000,4*1,VRAM
enddata
data2:
data C05_CCB,bgpal_work+$80,1,LOCAL
data C05_CBB,$0000,4*1,ADPCM
data C06A_PCB,bgpal_work+$80,1,LOCAL
data C06A_PBB,$2000,4*4,ADPCM
;MAPREG 4,$3d
data C06A_CAB,$8000,4*1,LOCAL
;MAPREG 5,$3e
;MAPREG 6,$3f
data C06A_CCB,sppal_work+$80,1,LOCAL
data C06A_CSB,$a000,4*1,LOCAL
data C06B_CSB,$c000,4*1,LOCAL
enddata
data3:
;MAPREG 4,$3a
data C07_CCB,bgpal_work,1,LOCAl
data C07_CBB,$8000,4*1,LOCAL
;MAPREG 5,$3b
data C08A_CCB,bgpal_work+$20,1,LOCAL
data C08A_CBB,$a000,4*1,LOCAL
;MAPREG 6,$3c
data C08B_CCB,sppal_work+$20,1,LOCAL
data C08B_CSB,$c000,4*1,LOCAL
data C09_CCB,bgpal_work+$40,1,LOCAL
data C09_CBB,$0000,4*1,ADPCM
data C010_CCB,bgpal_work+$60,1,LOCAL
data C010_CBB,$2000,4*1,ADPCM
data C012A1_CCB,sppal_work+$80,1,LOCAL
data C012A1_CSB,$4000,4*1,ADPCM
data C012A2_CSB,$6000,4*1,ADPCM
data C012B_PCB,bgpal_work+$80,1,LOCAL
data C012B_PBB,$8000,4*2,ADPCM
enddata
data4:
data C013E_CCB,bgpal_work,1,LOCAL
data C013E_CBB,$7000,4*1,VRAM
data C013D_CCB,sppal_work,1,LOCAL
data C013D_CSB,$6000,4*1,VRAM
data C013A_CCB,sppal_work+$20,1,LOCAL
data C013A_CSB,$5000,4*1,VRAM
data C013B_CSB,$2000,4*1,ADPCM
data C013C_CSB,$4000,4*1,ADPCM
data C014_PCB,bgpal_work+$40,1,LOCAL
data C014_PBB,$6000,4*2,ADPCM
data C015_PCB,bgpal_work+$60,1,LOCAL
data C015_PBB,$a000,4*3,ADPCM
enddata
data5:
data C016A_CCB,bgpal_work,1,LOCAL
data C016A_CBB,$7000,4*1,VRAM
data C016B_CCB,sppal_work,1,LOCAL
data C016B_CSB,$6000,4*1,VRAM
;MAPREG 4,$3a
data C017E_CCB,bgpal_work+$20,1,LOCAL
data C017E_CBB,$8000,4,LOCAL
;MAPREG 5,$3b
data C017A_CCB,sppal_work+$20,1,LOCAL
data C017A_CSB,$a000,4,LOCAL
enddata
data6:
;MAPREG 4,$3d
;MAPREG 5,$3e
;MAPREG 6,$3f
data C017B_CSB,$8000,4,LOCAL
data C017C_CSB,$a000,4,LOCAL
data C017D_CSB,$c000,4,LOCAL
data C018A_CCB,bgpal_work+$100,1,LOCAL
data C018A_CBB,$0000,4,ADPCM
data C018B_CBB,$2000,4,ADPCM
data C018C_CBB,$4000,4,ADPCM
data C018D_CBB,$6000,4,ADPCM
data C018E_CBB,$8000,4,ADPCM
data C018F_CBB,$a000,4,ADPCM
data C018G_CBB,$c000,4,ADPCM
data C018H_CBB,$e000,4,ADPCM
enddata
data7:
data C019_CCB,bgpal_work,1,LOCAL
data C019_CBB,$5000,4*1,VRAM
data C020_CCB,bgpal_work+$20,1,LOCAL
data C020_CBB,$4000,4*1,VRAM
;MAPREG 4,$3a
data C021A_CAB,$8000,4,LOCAL
;MAPREG 5,$3b
;MAPREG 6,$3c
data C021A_CCB,sppal_work+$40,1,LOCAL
data C021A_CSB,$a000,4,LOCAL
data C021B_CSB,$c000,4,LOCAL
data C022_CCB,bgpal_work+$60,1,LOCAL
data C022_CBB,$0000,4,ADPCM
data C023_PCB,bgpal_work+$80,1,LOCAL
data C023_PBB,$2000,4*4,ADPCM
enddata
ifdef audio
audio1:
audio at01_,NORMAL ;0
audio at02_,NORMAL ;1
audio at03_,NORMAL ;2
audio at04_,NORMAL ;3
audio at05_,NORMAL ;4
endif
startup:
;
; B01 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
read data1
mapreg 4,$3d
mapreg 5,$3e
mapreg 6,$3f
read data2
cdplay audio1,0
_@pe_bank #1
memset pal_bg,zero,$20
memset pal_sp,zero,$20
inc pal_flg
jsr win_flat
jsr dspon
_@fadein_start pal_bg,bgpal_work,pal_sp,sppal_work,1,7
_@fadein_wait _B99
_@wait 60*10,_b99
;
; B02 ================================================================
;
jsr dspoff
_@bg_bank #5,0,0
memcpy pal_bg,bgpal_work+$20,$20
inc pal_flg
jsr win_on
jsr dspon
_@wait 60*5,_b99
;
; B03 ================================================================
;
mapreg 5,$3b
trans $a000,$1000,$2000,MV
_@bg_bank #6,0,0
memcpy pal_bg,bgpal_work+$40,$20
memcpy pal_sp,sppal_work+$40,$20
inc pal_flg
_@anime_start #$3a,0,0,0,0
_@anime_wait _B99
_@wait 60*3,_b99
;
; B04 ================================================================
;
jsr dspoff
jsr sat_clr
_@bg_bank #7,0,0
memcpy pal_bg,bgpal_work+$60,$20
inc pal_flg
jsr dspon
_@wait 60*3,_B99
;
; B05 ================================================================
;
trans $0000,$3000,$2000,AV
_@bg_bank #3,0,0
memcpy pal_bg,bgpal_work+$60,$20
inc pal_flg
_@wait 60*5,_B99
;
; B06 ================================================================
;
trans $2000,$4000,$2000*4,AV
mapreg 5,$3e
mapreg 6,$3f
trans $a000,$1000,$2000*2,MV
jsr dspoff
_@pe_bank #4
_@anime_start #$3d,0,0,0,0
memcpy pal_bg,bgpal_work+$80,$20
memcpy pal_sp,sppal_work+$80,$20
inc pal_flg
jsr vsync
jsr dspon
_@wait 30,_B99
_@anime_wait _B99
_@wait 10,_B99
_@bgscrl_start 0,1,2
_@sprscrl_start 0,16,0,-1,2
_scrl_lp_B06:
_@wait 1,_B99
cmpiw bgy1,128
bne _scrl_lp_B06
_@bgscrl_stop
_@sprscrl_stop
cdwait _b99
;
; B07 ================================================================
;
MAPREG 4,$3a
MAPREG 5,$3b
MAPREG 6,$3c
read data3
cdplay audio1,1
jsr dspoff
stzw bgy1
mapreg 4,$3a
trans $8000,$1000,$2000,MV
jsr sat_clr
_@bg_bank #1,0,0
memcpy pal_bg,bgpal_work,$20
inc pal_flg
jsr dspon
_@wait 60*8,_b99
;
; B08 ================================================================
;
_B08:
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$2000,$2000*2,MV
jsr dspoff
_@bg_bank #2,0,0
_@sp_bank #3,0,0,0,128
memcpy pal_bg,bgpal_work+$20,$20
memcpy pal_sp,sppal_work+$20,$20
inc pal_flg
jsr dspon
_@wait 60*10,_b99
;
; B09 ================================================================
;
_B09:
trans $0000,$1000,$2000,AV
jsr sat_clr
_@bg_bank #1,0,0
memcpy pal_bg,bgpal_work+$40,$20
inc pal_flg
_@wait 60*10,_B99
;
; B10 ================================================================
;
_B10:
trans $2000,$2000,$2000,AV
_@bg_bank #2,0,0
memcpy pal_bg,bgpal_work+$60,$20
inc pal_flg
_@wait 60*8,_B99
;
; B11 ================================================================
;
_B11:
jsr bgpal_clr
jsr sat_clr
_@wait 60*1,_B99
;
; B12 ================================================================
;
_B12:
trans $4000,$1000,$2000*4,AV
jsr bgpal_clr
jsr sppal_clr
_@pe_bank #3
_@sp_bank #1,0,-128,0,0
_@sp_bank #2,0,0,0,128
_@fadein_start pal_bg,bgpal_work+$80,pal_sp,sppal_work+$80,1,7
_@sprscrl_start 0,32,0,2,2
_scrl_lp_B12_a:
_@wait 1,_B99
cmpiw2 sprscrl_count,(128+64)/2
bcc _scrl_lp_B12_a
_@sprscrl_stop
_@fadein_wait _B99
_@wait 60*1,_B99
_@bgscrl_start 1,0,2
_scrl_lp_B12_b:
_@wait 1,_B99
cmpiw bgx1,128
bne _scrl_lp_B12_b
_@bgscrl_stop
_@wait 60*3,_B99
cdwait _b99
;
; B13 ================================================================
;
read data4
cdplay audio1,2
jsr dspoff
stzw bgx1
_@bg_bank #7,0,0
_@sp_bank #6,0,0,0,128
_@sp_bank #5,0,0,1,0
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work,$40
inc pal_flg
jsr dspon
_@wait 4,_B99
trans $2000,$4000,$2000,AV
_@sp_bank #4,0,0,1,0
_@wait 4,_B99
trans $4000,$5000,$2000,AV
_@sp_bank #5,0,0,1,0
_@wait 60*8,_B99
;
; B14 ================================================================
;
trans $6000,$1000,$2000*2,AV
jsr dspoff
jsr sat_clr
_@pe_bank #1
memcpy pal_bg,bgpal_work+$40,$20
inc pal_flg
jsr win_flat
jsr dspon
_@wait 60*2,_B99
;
; B15 ================================================================
;
trans $a000,$3000,$2000*3,AV
jsr dspoff
moviw bgy1,32
_@pe_bank #3
memcpy pal_bg,bgpal_work+$60,$20
inc pal_flg
jsr win_on
jsr dspon
_@wait 60*1,_B99
_@bgscrl_start 1,0,4
_scrl_lp_B15:
_@wait 1,_B99
cmpiw bgx1,128
bne _scrl_lp_B15
_@bgscrl_stop
_@wait 60*2,_B99
cdwait _b99
;
; B16 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
read data5
mapreg 4,$3d
mapreg 5,$3e
mapreg 6,$3f
read data6
cdplay audio1,3
jsr dspoff
stzw bgx1
stzw bgy1
_@bg_bank #7,0,0
_@sp_bank #6,0,128,0,128
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work,$20
inc pal_flg
jsr dspon
_@wait 60,_B99
_@sprscrl_start 16,16,0,-1,2
_scrl_lp_B16:
_@wait 1,_B99
cmpiw2 sprscrl_count,128
bcc _scrl_lp_B16
_@sprscrl_stop
_@wait 60*3,_B99
;
; B17 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
trans $8000,$4000,$2000*2,MV
mapreg 4,$3d
trans $8000,$3000,$2000,MV
_@bg_bank #4,0,0
_@sp_bank #5,0,0,0,128
_@sp_bank #3,0,0,1,0
memcpy pal_bg,bgpal_work+$20,$20
memcpy pal_sp,sppal_work+$20,$40
inc pal_flg
_@wait 30,_B99
mapreg 5,$3e
trans $a000,$2000,$2000,MV
_@sp_bank #2,0,0,1,0
_@wait 10,_B99
mapreg 6,$3f
trans $c000,$3000,$2000,MV
_@sp_bank #3,0,0,1,0
_@wait 60*1,_B99
memcpy pal_sp,sppal_work+$20,$20 ;0
inc pal_flg
_@wait 10,_B99
memcpy pal_sp,sppal_work+$40,$20 ;1
inc pal_flg
_@wait 10,_B99
memcpy pal_sp,sppal_work+$60,$20 ;2
inc pal_flg
_@wait 10,_B99
memcpy pal_sp,sppal_work+$80,$20 ;3
inc pal_flg
_@wait 10,_B99
memcpy pal_sp,sppal_work+$60,$20 ;2
inc pal_flg
_@wait 60*6,_B99
;
; B18 ================================================================
;
trans $0000,$6000,$2000,AV
jsr dspoff
jsr sat_clr
_@wait 7,_B99
_@bg_bank #6,0,0
memcpy pal_bg,bgpal_work+$100,$20
inc pal_flg
jsr dspon
trans $2000,$7000,$2000,AV
_@bg_bank #7,0,0
trans $4000,$6000,$2000,AV
_@bg_bank #6,0,0
trans $6000,$7000,$2000,AV
_@bg_bank #7,0,0
trans $8000,$6000,$2000,AV
_@bg_bank #6,0,0
trans $a000,$7000,$2000,AV
_@bg_bank #7,0,0
trans $c000,$6000,$2000,AV
_@bg_bank #6,0,0
trans $e000,$7000,$2000,AV
_@bg_bank #7,0,0
_@wait 7,_B99
jsr bgpal_clr
_@wait 60,_B99
cdwait _b99
;
; B19 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
read data7
cdplay audio1,4
_@bg_bank #5,0,0
_@fadein_start pal_bg,bgpal_work,pal_sp,sppal_work,1,7
_@fadein_wait _B99
_@wait 60*5,_B99
;
; B20 ================================================================
;
_@bg_bank #4,0,0
memcpy pal_bg,bgpal_work+$20,$20
inc pal_flg
_@wait 60*5,_B99
;
; B21 ================================================================
;
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$1000,$2000*2,MV
_@anime_start #$3a,0,0,0,0
memcpy pal_bg,bgpal_work+$40,$20
memcpy pal_sp,sppal_work+$40,$20
inc pal_flg
jsr vsync
_@anime_wait _B99
;
; B22 ================================================================
;
trans $0000,$7000,$2000,AV
jsr dspoff
jsr sat_clr
_@bg_bank #7,0,0
memcpy pal_bg,bgpal_work+$60,$20
inc pal_flg
jsr vsync
jsr dspon
_@wait 60*5,_b99
;
; B23 ================================================================
;
trans $2000,$3000,$2000*4,AV
jsr dspoff
_@pe_bank #3
memcpy pal_bg,bgpal_work+$80,$20
inc pal_flg
_@palc_start pal_bg,bgpal_work+$80,bgpal_work+$a0,2
_@wait 10,_B99
ldx #2
_lplp:
phx
moviw bgy1,128
jsr dspon
jsr vsync
_@bgscrl_start 0,-8,3
_scrl_lp_B23_a:
_@wait 1,_B99
cmpiw bgy1,0
bne _scrl_lp_B23_a
_@bgscrl_stop
plx
dex
jne _lplp
moviw bgy1,128
_@bgscrl_start 0,-4,3
_scrl_lp_B23_b:
_@wait 1,_B99
cmpiw bgy1,0
bne _scrl_lp_B23_b
_@bgscrl_stop
_@wait 60*2,_B99
cdwait _b99
_@fadeout_start pal_bg,pal_sp,1,7
_@fadeout_wait _B99
;
; B99 ================================================================
;
jsr dspoff
jsr bgpal_clr
jsr sppal_clr
jsr sat_clr
_B99:
jsr all_done
sei
clx
_move_lp:
lda $3f00,x
sta $2000,x
inx
bne _move_lp
CDEXEC AXE_BIN,$4000,1
;
endChunk 9#
;
; AX BATTLER (Opening)
;
include macro.h
include visual.h
include biosw.h
include c62.h
include uty.h
include inf_c.h
;
player equ $2000
stage equ $2001
player_s equ $3f00
stage_s equ $3f01
mode equ $3ffe
;
public entry
;
seg dseg
sppal_work ds 2048+$100
bgpal_work ds 2048+$100
subcode_buff ds 10
seg cseg
entry:
jmp startup
data1:
data C1_PCB,bgpal_work,1,LOCAL
data C1_PBB,$6000,4*2,VRAM
;MAPREG 4,$3a
data C2A_CAB,$8000,4,LOCAL
data C2D_CCB,sppal_work+$20,1,LOCAL
data C2D_CSB,$1000,4,VRAM
data C2E_CSB,$2000,4,VRAM
data C2F_CSB,$3000,4,VRAM
data C2G_CSB,$4000,4,VRAM
;MAPREG 5,$3b
data C2C_CCB,sppal_work+$40,1,LOCAL
data C2C_CSB,$a000,4,LOCAL
;MAPREG 6,$3c
data C2B_CCB,bgpal_work+$20,1,LOCAL
data C2B_CBB,$c000,4,LOCAL
enddata
data2:
data C3B1_CCB,bgpal_work+$60,1,LOCAL
data C3B1_CBB,$0000,4,ADPCM
data C3B2_CBB,$2000,4,ADPCM
;MAPREG 4,$3d
data C3A_CAB,$8000,4,LOCAL
;MAPREG 5,$3e
;MAPREG 6,$3f
data C3C_CCB,sppal_work+$60,1,LOCAL
data C3C_CSB,$a000,4*1,LOCAL
data C3D_CSB,$c000,4*1,LOCAL
enddata
data3:
;MAPREG 4,$3a
data C5A_CAB,$8000,4,LOCAL
;MAPREG 5,$3b
data C5B_CCB,bgpal_work,1,LOCAL
data C5B_CBB,$a000,4,LOCAL
data C5D_CCB,sppal_work,1,LOCAL
data C5D_CSB,$2000,4,ADPCM
data C5E_CSB,$4000,4,ADPCM
data C5C_CCB,sppal_work+$20,1,LOCAL
data C5C_CSB,$0000,4,ADPCM
enddata
data4:
;MAPREG 4,$3d
data C6A_CAB,$8000,4,LOCAL
;MAPREG 5,$3e
data C6F_CCB,bgpal_work+$40,1,LOCAL
data C6F_CBB,$a000,4,LOCAL
data C6B_CCB,sppal_work+$40,1,LOCAL
data C6B_CSB,$6000,4,ADPCM
data C6C_CSB,$8000,4,ADPCM
data C6D_CSB,$a000,4,ADPCM
data C6E_CSB,$c000,4,ADPCM
data C7_CCB,bgpal_work+$60,1,LOCAL
data C7_CBB,$e000,4,ADPCM
enddata
data5:
data C8A_PCB,bgpal_work+$20,1,LOCAL
data C8A_PBB,$5000,4*2,VRAM
data C8C1_CCB,sppal_work+$20,1,LOCAL
data C8C1_CSB,$3000,4,VRAM
data C8C2_CSB,$4000,4,VRAM
_C09_read:
;MAPREG 4,$3a
data C9A_CAB,$8000,4,LOCAL
;MAPREG 5,$3b
data C9B_CCB,bgpal_work+$40,1,LOCAL
data C9B_CBB,$a000,4,LOCAL
data C9C_CCB,sppal_work+$40,1,LOCAL
data C9C_CSB,$0000,4,ADPCM
data C9D_CSB,$2000,4,ADPCM
data C9E_CSB,$4000,4,ADPCM
data C9F_CSB,$6000,4,ADPCM
enddata
data6:
;MAPREG 4,$3d
;MAPREG 5,$3e
data C10B1_CCB,sppal_work+$60,1,LOCAL
data C10B1_CSB,$8000,4,LOCAL
data C10B2_CSB,$a000,4,LOCAL
data C10A_PCB,bgpal_work+$60,1,LOCAL
data C10A_PBB,$8000,4*4,ADPCM
enddata
data7:
data C11C_PCB,bgpal_work,1,LOCAL
data C11C_PBB,$0000,4*2,ADPCM
data C11A_CCB,sppal_work,1,LOCAL
data C11A_CSB,$c000,4,ADPCM
data C11B_CCB,sppal_work+$20,1,LOCAL
data C11B_CSB,$e000,4,ADPCM
;MAPREG 4,$3a
data C12A_CAB,$8000,4,LOCAL
;MAPREG 5,$3b
;MAPREG 6,$3c
data C12B_CCB,sppal_work+$40,1,LOCAL
data C12B_CSB,$a000,4,LOCAL
data C12C_CSB,$c000,4,LOCAL
enddata
data8:
;MAPREG 4,$3d
data C12AA_CAB,$8000,4,LOCAL
data C12BB_CCB,sppal_work+$60,1,LOCAL
data C12BB_CSB,$4000,4,ADPCM
data C12CC_CSB,$6000,4,ADPCM
data C12DD_CSB,$8000,4,ADPCM
data C12A_CCB,bgpal_work+$60,1,LOCAL
data C12A_CBB,$a000,4,ADPCM
enddata
data9:
;MAPREG 4,$3a
data C13A_CAB,$8000,4,LOCAL
;MAPREG 5,$3b
;MAPREG 6,$3c
data C13B_CCB,sppal_work+$60,1,LOCAL
data C13B_CSB,$a000,4,LOCAL
data C13C_CSB,$c000,4,LOCAL
data C14XA_CAB,$0000,4,ADPCM
data C14XA1_CCB,sppal_work+$80,1,LOCAL
data C14XA1_CSB,$2000,4,ADPCM
data C14XA2_CSB,$4000,4,ADPCM
data C14XB_CAB,$6000,4,ADPCM
data C14XB1_CCB,sppal_work+$a0,1,LOCAL
data C14XB1_CSB,$8000,4,ADPCM
data C14XB2_CSB,$a000,4,ADPCM
data C14XD1_CCB,bgpal_work+$80,1,LOCAL
data C14XD1_CBB,$c000,4,ADPCM
data C14XD2_CBB,$e000,4,ADPCM
enddata
data10:
data C14AA_CCB,bgpal_work+$100,1,LOCAL
data C14AA_CBB,$7000,4,VRAM
;MAPREG 4,$3d
data C14AA_CAB,$8000,4,LOCAL
;MAPREG 5,$3e
;MAPREG 6,$3f
data C14BB_CCB,sppal_work+$100,1,LOCAL
data C14BB_CSB,$a000,4,LOCAL
data C14CC_CSB,$c000,4,LOCAL
enddata
data11:
;MAPREG 4,$3a
data C15A_CAB,$8000,4,LOCAL
data C15B_CCB,sppal_work,1,LOCAL
data C15B_CSB,$0000,4,ADPCM
data C15C_CSB,$2000,4,ADPCM
data C15D_CCB,bgpal_work,1,LOCAL
data C15D_CBB,$4000,4,ADPCM
;MAPREG 5,$3b
data C15E_CCB,sppal_work+$20,1,LOCAL
data C15E_CSB,$a000,4,LOCAL
enddata
data12:
;MAPREG 4,$3d
data C16A_CAB,$8000,4,LOCAL
;MAPREG 5,$3e
;MAPREG 6,$3f
data C16B_CCB,sppal_work+$40,1,LOCAL
data C16B_CSB,$a000,4,LOCAL
data C16C_CSB,$c000,4,LOCAL
enddata
ifdef audio
audio1:
audio ab01_,NORMAL ;0
audio ab02_,NORMAL ;1
audio ab03_,NORMAL ;2
audio ab04_,NORMAL ;3
audio ab05_,NORMAL ;4
audio ab06_,NORMAL ;5
endif
startup:
;
; C01 ================================================================
;
MAPREG 4,$3a
MAPREG 5,$3b
MAPREG 6,$3c
read data1
MAPREG 4,$3d
MAPREG 5,$3e
MAPREG 6,$3f
read data2
cdplay audio1,0
moviw bgx1,128
_@pe_bank #6
memset pal_bg,zero,$20
memset pal_sp,zero,$20
inc pal_flg
jsr win_on
jsr dspon
_@fadein_start pal_bg,bgpal_work,pal_sp,sppal_work,1,7
_@fadein_wait _C99
_@bgscrl_start -1,0,2
_scrl_lp_C01:
_@wait 1,_C99
cmpiw bgx1,0
bne _scrl_lp_C01
_@bgscrl_stop
_@wait 60*3,_C99
;
; C02 ================================================================
;
jsr dspoff
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$5000,$2000*2,MV
stzw bgx1
_@bg_bank #6,0,0
_@sp_bank #5,0,0,0,0
memcpy pal_bg,bgpal_work+$20,$20
memcpy pal_sp,sppal_work+$20,$40
inc pal_flg
jsr win_on
jsr dspon
_@anime_start #$3a,0,0,128,0
_@anime_wait _C99
;
; C03 ================================================================
;
jsr dspoff
trans $0000,$5000,$2000*2,AV
mapreg 5,$3e
mapreg 6,$3f
trans $a000,$1000,$2000*2,MV
jsr sat_clr
_@bg_bank #5, 0,0
_@bg_bank #6,16,0
_@bg_bank #5,32,0
_@bg_bank #6,48,0
_@anime_start #$3d,0,0,0,1
memcpy pal_bg,bgpal_work+$60,$20
memcpy pal_sp,sppal_work+$60,$20
inc pal_flg
jsr vsync
jsr dspon
_@bgscrl_start 1,0,6
;
; C04 ================================================================
;
; nop
cdwait _c99
;
; C05 ================================================================
;
MAPREG 4,$3a
MAPREG 5,$3b
read data3
MAPREG 4,$3d
MAPREG 5,$3e
read data4
_@anime_stop
_@bgscrl_stop
cdplay audio1,1
jsr dspoff
mapreg 5,$3b
trans $a000,$4000,$2000,MV
trans $0000,$1000,$2000*3,AV
stzw bgx1
stzw bgy1
_@bg_bank #4,0,0
_@sp_bank #1,0,0,1,128
_@anime_start #$3a,0,0,0,1
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work,$40
inc pal_flg
jsr vsync
jsr dspon
_@wait 60*5,_C99
_@anime_stop
;
; C06 ================================================================
;
jsr dspoff
mapreg 5,$3e
trans $a000,$6000,$2000,MV
trans $6000,$1000,$2000*4,AV
jsr sat_clr
_@bg_bank #6,0,0
inc animate_bnum
_@anime_start #$3d,0,0,128,0
memset pal_bg,zero,$20
memset pal_sp,zero,$20
inc pal_flg
jsr vsync
jsr dspon
_@fadein_start pal_bg,bgpal_work+$40,pal_sp,sppal_work+$40,1,7
_@fadein_wait _C99
_@anime_wait _C99
_@wait 60*5,_c99
stz animate_bnum
;
; C07 ================================================================
;
trans $e000,$7000,$2000,AV
jsr dspoff
jsr sat_clr
_@bg_bank #7,0,0
memset pal_bg,zero,$20
inc pal_flg
jsr dspon
memcpy bgpal_work,bgpal_work+$60,$20
_@fadein_start pal_bg,bgpal_work,pal_sp,sppal_work,1,7
cdwait _c99
;
; C08 ================================================================
;
MAPREG 4,$3a
MAPREG 5,$3b
read data5
MAPREG 4,$3d
MAPREG 5,$3e
read data6
_@fadein_wait _C99
cdplay audio1,2
jsr dspoff
moviw bgx1,128
_@pe_bank #5
_@sp_bank #3,-128,0,0,128
_@sp_bank #4, 0,0,0,128+64
memcpy pal_bg,bgpal_work+$20,$20
memcpy pal_sp,sppal_work+$20,$20
inc pal_flg
jsr dspon
_@sprscrl_start 16,16,1,0,2
_@bgscrl_start -1,0,2
_scrl_lp_C08:
_@wait 1,_C99
cmpiw bgx1,0
bne _scrl_lp_C08
_@sprscrl_stop
_@bgscrl_stop
_@wait 60*15,_c99
;
; C09 ================================================================
;
jsr dspoff
mapreg 5,$3b
trans $a000,$7000,$2000,MV
trans $0000,$1000,$2000*4,AV
stzw bgx1
jsr sat_clr
_@bg_bank #7,0,0
_@anime_start #$3a,0,0,0,0
memcpy pal_bg,bgpal_work+$40,$20
memcpy pal_sp,sppal_work+$40,$20
inc pal_flg
jsr vsync
jsr dspon
_@anime_wait _C99
_@wait 60*5,_c99
;
; C10 ================================================================
;
jsr dspoff
trans $8000,$4000,$2000*4,AV
mapreg 4,$3d
mapreg 5,$3e
trans $8000,$2000,$2000*2,MV
moviw bgy1,128
jsr sat_clr
_@pe_bank #4
_@sp_bank #2,0,-128,0,128
_@sp_bank #3,0, 0,0,128+64
memcpy pal_bg,bgpal_work+$60,$20
memcpy pal_sp,sppal_work+$60,$20
inc pal_flg
jsr dspon
_@sprscrl_start 16,16,0,1,2
_@bgscrl_start 0,-1,2
_scrl_lp_C10:
_@wait 1,_C99
cmpiw bgy1,0
bne _scrl_lp_C10
_@sprscrl_stop
_@bgscrl_stop
_@wait 60,_C99
cdwait _c99
;
; C11 ================================================================
;
MAPREG 4,$3a
MAPREG 5,$3b
MAPREG 6,$3c
read data7
MAPREG 4,$3d
read data8
cdplay audio1,3
jsr dspoff
stzw bgx1
stzw bgy1
trans $0000,$6000,$2000*2,AV
trans $c000,$4000,$2000*2,AV
jsr sat_clr
_@pe_bank #6
_@sp_bank #4,0,0,0,128
_@sp_bank #5,128,0,1,128+64
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work,$40
inc pal_flg
jsr dspon
_@wait 60,_C99
_@sprscrl_start 16,16,-1,0,4
_@bgscrl_start 1,0,4
_scrl_lp_C11:
_@wait 1,_C99
cmpiw bgx1,128
bne _scrl_lp_C11
_@sprscrl_stop
_@bgscrl_stop
_@wait 60*3,_C99
;
; C12 ================================================================
;
jsr dspoff
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$1000,$2000*2,MV
stzw bgx1
jsr sat_clr
_@anime_start #$3a,0,0,0,0
memcpy pal_sp,sppal_work+$40,$20
inc pal_flg
jsr vsync
jsr dspon
_@anime_wait _C99
;
; C12b ================================================================
;
_C12b:
memcpy bgpal_work,bgpal_work+$60,$40
memcpy sppal_work,sppal_work+$60,$40
jsr dspoff
trans $4000,$1000,$2000*4,AV
jsr sat_clr
_@bg_bank #4,0,0
_@anime_start #$3d,128,0,0,1
_@palc_start pal_bg,bgpal_work,bgpal_work+$20,2
memcpy pal_sp,sppal_work,$20
inc pal_flg
jsr dspon
_@wait 30,_C99
_@sprscrl_start 0,16,-1,0,2
_scrl_lp_C12:
_@wait 2,_C99
decw animate_x
cmpiw sprscrl_count,128
cmpiw animate_x,0
bne _scrl_lp_C12
_@sprscrl_stop
_@wait 60,_C99
cdwait _c99
_@anime_stop
;
; C13 ================================================================
;
MAPREG 4,$3a
MAPREG 5,$3b
MAPREG 6,$3c
read data9
MAPREG 4,$3d
MAPREG 5,$3e
MAPREG 6,$3f
read data10
_@palc_stop
cdplay audio1,4
jsr dspoff
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$1000,$2000*2,MV
jsr sat_clr
_@anime_start #$3a,0,0,0,0
memcpy pal_sp,sppal_work+$60,$20
inc pal_flg
jsr vsync
jsr dspon
_@anime_wait _C99
;
; C14 ================================================================
;
mapreg 4,$3a
trans $0000,$8000,$2000,AM
mapreg 5,$3b
trans $6000,$a000,$2000,AM
jsr dspoff
trans $2000,$1000,$2000*2,AV
trans $8000,$3000,$2000*2,AV
trans $c000,$5000,$2000*2,AV
stzw bgx1
_@bg_bank #5,0,0
_@bg_bank #6,16,0
inc animate_bnum
_@anime_start #$3a,0,0,128,0
memcpy pal_bg,bgpal_work+$80,$40
memcpy pal_sp,sppal_work+$80,$40
inc pal_flg
jsr win_on
jsr win_flat
jsr vsync
jsr dspon
_@wait 60*2,_C99
_@anime_wait _C99
stz animate_bnum
;
; C14b ================================================================
;
jsr dspoff
mapreg 5,$3e
mapreg 6,$3f
trans $a000,$1000,$2000*2,MV
stzw bgx1
stzw bgy1
jsr sat_clr
_@bg_bank #7,0,0
_@anime_start #$3d,0,0,0,0
memcpy pal_bg,bgpal_work+$100,$20
memcpy pal_sp,sppal_work+$100,$20
inc pal_flg
jsr win_on
jsr vsync
jsr dspon
_@anime_wait _C99
cdwait _c99
;
; C15 ================================================================
;
MAPREG 4,$3a
MAPREG 5,$3b
MAPREG 6,$3c
read data11
MAPREG 4,$3d
MAPREG 5,$3e
MAPREG 6,$3f
read data12
cdplay audio1,5
jsr dspoff
trans $0000,$1000,$2000*3,AV
mapreg 5,$3b
trans $a000,$4000,$2000,MV
jsr sat_clr
_@bg_bank #3,0,0
_@sp_bank #4,0,0,1,0
_@anime_start #$3a,0,0,128,0
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work,$40
inc pal_flg
jsr vsync
jsr dspon
_@anime_wait _C99
_@wait 60*16,_c99
;
; C16 ================================================================
;
jsr dspoff
mapreg 5,$3e
mapreg 6,$3f
trans $a000,$1000,$2000*2,MV
jsr sat_clr
_@anime_start #$3d,0,0,0,0
memset pal_bg,zero,$20
memcpy pal_sp,sppal_work+$40,$20
inc pal_flg
jsr dspon
_@anime_wait _C99
_@wait 60,_C99
cdwait _c99
_@fadeout_start pal_bg,pal_sp,1,7
_@fadeout_wait _C99
;
; C99 ================================================================
;
jsr dspoff
jsr bgpal_clr
jsr sppal_clr
jsr sat_clr
_C99:
jsr all_done
sei
clx
_move_lp:
lda $3f00,x
sta $2000,x
inx
bne _move_lp
CDEXEC AXE_BIN,$4000,1
;
endChunk 10#
;
include biosw.h
include c62.h
include macro.h
;
extern regbox
extern ad_read2
;
audiof equ $3ffc
visualf equ $3ffd
;
seg zseg
public rec_adr,xlat_s,xlat_d,xlat_l
rec_adr ds 2
xlat_s ds 2
xlat_d ds 2
xlat_l ds 2
;
seg dseg
public subq_buf
subq_buf ds 10
;
seg cseg
;
; in. rec_adr data table addr: refer data_table
;
public data_read
data_read:
cly
_read_data:
lda [rec_adr],y
beq _adtrans
cmp #99
beq _done
_cdread:
sta _dh ;mode
iny
lda [rec_adr],y
sta _cl ;record_hi
iny
lda [rec_adr],y
sta _ch ;high(record_lw)
iny
lda [rec_adr],y
sta _dl ;low(record_lw)
iny
lda [rec_adr],y
sta _al ;record_rl
iny
lda [rec_adr],y
sta _bl ;low(dst_adr)
iny
lda [rec_adr],y
sta _bh ;high(dst_adr)
phy
jsr cd_read
ply
iny
bra _read_data
_adtrans:
sta _dh ;mode
iny
lda [rec_adr],y
sta _cl ;record_hi
iny
lda [rec_adr],y
sta _ch ;high(record_lw)
iny
lda [rec_adr],y
sta _dl ;low(record_lw)
iny
lda [rec_adr],y
sta _al ;record_rl
iny
lda [rec_adr],y
sta _bl ;low(dst_adr)
iny
lda [rec_adr],y
sta _bh ;high(dst_adr)
phy
jsr ad_trans
ply
iny
bra _read_data
_done:
rts
;
; in. AREG (mode: $00 = ad->local, $ff = ad->vram, $01 = ram->vram)
;
public data_trans
data_trans:
dec a
beq _from_local
_from_ad:
inc a
sta _dh ;mode
lda xlat_s
sta _cl
lda xlat_s+1
sta _ch
lda xlat_d
sta _bl
lda xlat_d+1
sta _bh
lda xlat_l
sta _al
lda xlat_l+1
sta _ah
jsr ad_read2
cmp $00
bne _from_ad
bra _trans_done
_from_local:
lda xlat_l+1
lsr a
tay
_lplp1:
phy
clx
_lplp2:
phx
setreg MAWR
outmw xlat_d
setreg VWR
lda [xlat_s]
sta LOW7UP
incw xlat_s
lda [xlat_s]
sta HI7UP
incw xlat_s
incw xlat_d
plx
dex
bne _lplp2
ply
dey
bne _lplp1
_trans_done:
rts
;
; in. AREG music num: refer audio_table
;
public play_audio
play_audio:
;; lda audiof
;; beq _fail
pha
cla
jsr cd_fade
pla
asl a
asl a
asl a
tay
lda [rec_adr],y
inc a
beq _fail
iny
lda [rec_adr],y ;mode
sta _dh
iny
lda #$40
sta _bh
lda [rec_adr],y ;AMIN
sta _al
iny
lda [rec_adr],y ;ASEC
sta _ah
iny
lda [rec_adr],y ;AFRAME
sta _bl
iny
lda [rec_adr],y ;AMIN
sta _cl
iny
lda [rec_adr],y ;ASEC
sta _ch
iny
lda [rec_adr],y ;AFRAME
sta _dl
jsr cd_play
_fail:
rts
;
;
;
public stop_audio
stop_audio:
lda #%1100_0000
sta _bh
lda #%1100_0000
sta _dh
jsr cd_play
cla
jsr cd_fade
rts
;
; out. AREG (playing status)
;
public audio_stat
audio_stat:
lda #low(subq_buf)
sta _bl
lda #high(subq_buf)
sta _bh
jsr cd_subq
lda subq_buf
rts
public audio_wait
audio_wait:
lda #low(subq_buf)
sta _bl
lda #high(subq_buf)
sta _bh
jsr cd_subq
lda subq_buf
bne audio_wait
rts
;
; fade out
;
public fade_audio
fade_audio:
;; lda audiof
;; beq _fail2
lda #$0C
jsr cd_fade
_fail2:
rts
;audio_tbl:
; audio title_,REPEAT ;0
; audio s01_,NORMAL ;1
; audio s02_,NORMAL ;2
; audio s03_,NORMAL ;3
; audio s05_,NORMAL ;4
; audio s07_,NORMAL ;5
; audio s09_,NORMAL ;6
; audio s10_,NORMAL ;7
; audio s13_,NORMAL ;8
; audio s14_,NORMAL ;9
; audio s15_,NORMAL ;10
; audio s17_,NORMAL ;11
; audio s18_,NORMAL ;12
; audio s19_,NORMAL ;13
;
public reset_mpr
reset_mpr:
lda max_mapping
tam2
inc a
tam3
inc a
tam4
inc a
tam5
inc a
tam6
rts
public adjust_mpr
adjust_mpr:
sec
sbc #$38
clc
adc max_mapping
rts
public dummy_irq
dummy_irq:
lda #$40
sta $200f
lda #$01
ldx #low ($200f)
ldy #high ($200f)
jsr ex_setvec
lda #%0000_0010
sta irq_m
rts
endChunk 11#
;
; DEATH ADDER (Opening)
;
include macro.h
include visual.h
include biosw.h
include c62.h
include uty.h
include inf_a.h
;
stage equ $3f00
player equ $3f01
mode equ $3ffe
;
public entry
;
seg dseg
bgpal_work ds 2048+$300
sppal_work ds 2048+$200
seg cseg
entry:
jmp startup
data1: data DOC1_PCB,bgpal_work,1,LOCAL
data DOC1_PBB,$1000,4*4,VRAM
data C2_PCB,bgpal_work+$100,1,LOCAL
data C2_PBB,$5000,4*2,VRAM
data C3_CCB,bgpal_work+$200,1,LOCAL
data C3_CBB,$0000,4*1,ADPCM
enddata
data2: ;MAPREG 4,$3a
data C4_CCB,bgpal_work,1,LOCAL
data C4_CBB,$8000,4*1,LOCAL
data C4A_CCB,sppal_work,1,LOCAL
data C4A_CSB,$1000,4*1,VRAM
data C4B_CSB,$2000,4*1,VRAM
data C4C_CSB,$3000,4*1,VRAM
data C5_PCB,bgpal_work+$20,1,LOCAL
data C5_PBB,$4000,4*2,VRAM
enddata
data3: ;MAPREG 4,$3d
;MAPREG 5,$3e
;MAPREG 6,$3f
data C5A_CAB,$8000,4*1,LOCAL
data C5A_CCB,sppal_work+$20,1,LOCAL
data C5A_CSB,$a000,4*1,LOCAL
enddata
data6: data C6A_CCB,bgpal_work,1,LOCAL
data C6A_CBB,$6000,4*1,VRAM
data C6B_CCB,sppal_work,1,LOCAL
data C6B_CSB,$7000,4*1,VRAM
data C7A_CCB,bgpal_work+$100,1,LOCAL
data C7A_CBB,$3000,4*1,VRAM
;MAPREG 4,$3a
;MAPREG 5,$3b
;MAPREG 6,$3c
data C7A_CAB,$8000,4*1,LOCAL
data C7B_CCB,sppal_work+$100,1,LOCAL
data C7B_CSB,$a000,4*1,LOCAL
data C7C_CSB,$c000,4*1,LOCAL
enddata
data8: data C8A_CCB,bgpal_work,1,LOCAL
data C8A_CBB,$4000,4*1,VRAM
;MAPREG 4,$3a
;MAPREG 5,$3b
;MAPREG 6,$3c
data C8A_CAB,$8000,4*1,LOCAL
data C8B_CCB,sppal_work,1,LOCAL
data C8B_CSB,$a000,4*1,LOCAL
data C8C_CSB,$c000,4*1,LOCAL
data C8D_CSB,$0000,4*1,ADPCM
enddata
data9: data C9A_CCB,bgpal_work+$100,1,LOCAL
data C9A_CBB,$5000,4*1,VRAM
;MAPREG 4,$3d
;MAPREG 5,$3e
;MAPREG 6,$3f
data C9A_CAB,$8000,4*1,LOCAL
data C9B_CCB,sppal_work+$100,1,LOCAL
data C9B_CSB,$a000,4*1,LOCAL
data C9C_CSB,$c000,4*1,LOCAL
enddata
data10:
data C10A_CCB,bgpal_work+$200,1,LOCAL
data C10A_CBB,$6000,4,VRAM
data C10AA_CAB,$2000,4,ADPCM ;an
data C10BB_CCB,sppal_work+$200,1,LOCAL
data C10BB_CSB,$4000,4,ADPCM
data C10CC_CSB,$6000,4,ADPCM
data C10B_CCB,sppal_work+$220,1,LOCAL
data C10B_CSB,$8000,4,ADPCM
data C10C_CSB,$a000,4,ADPCM
data C10D_CSB,$c000,4,ADPCM
enddata
data11:
data C11_CCB,bgpal_work,1,LOCAL
data C11_CBB,$3000,4,VRAM
data C12_CCB,sppal_work+$100,1,LOCAL
data C12_CSB,$4000,4,VRAM
;MAPREG 5,$3b
;MAPREG 6,$3c
data C12A_CCB,sppal_work+$120,1,LOCAL
data C12A_CSB,$a000,4*1,LOCAL
data C12B_CSB,$c000,4*1,LOCAL
enddata
data13: ;MAPREG 5,$3e
data C13_CCB,bgpal_work+$200,1,LOCAL
data C13_CBB,$a000,4*1,LOCAL
data C14A_PCB,bgpal_work+$300,1,LOCAL
data C14A_PBB,$0000,4*3,ADPCM
data C14B1_CCB,sppal_work+$200,1,LOCAL
data C14B1_CSB,$6000,4,ADPCM
data C14B2_CSB,$8000,4,ADPCM
data C14B3_CSB,$a000,4,ADPCM
data C14B4_CSB,$c000,4,ADPCM
enddata
ifdef audio
audio1:
audio ad01_,NORMAL ;0
audio ad02_,NORMAL ;1
audio ad03_,NORMAL ;2
audio ad04_,NORMAL ;3
endif
startup:
;
; A01 ================================================================
;
jsr dspoff
read data1
cdplay audio1,0
_@pe_bank #1
memcpy pal_bg,bgpal_work,$20
inc pal_flg
jsr win_off
jsr dspon
ldx #2
_thunder_lp_a01:
phx
_@wait 60*2,_a99
moviw thunder_base,$e0
jsr thunder
plx
dex
jne _thunder_lp_a01
_@wait 60*1,_a99
;
; A02 ================================================================
;
moviw bgy1,-64
memcpy bgpal_work,bgpal_work+$100,$100
_@pe_bank #5
_@bg_bank #7,0,16
_@bg_bank #7,16,16
memcpy pal_bg,bgpal_work+$e0,$20
inc pal_flg
jsr vsync
moviw thunder_base,$e0
jsr thunder
_@wait 60*2,_a99
;
; A03 ================================================================
;
jsr dspoff
stzw bgx1
stzw bgy1
trans $0000,$7000,$2000,AV
memcpy bgpal_work,bgpal_work+$200,$100
_@bg_bank #7,0,0
memcpy pal_bg,bgpal_work,$20
inc pal_flg
jsr win_on
jsr dspon
_@wait 60*2,_a99
moviw thunder_base,$e0
jsr thunder
_@wait 60*2,_a99
cdwait _a99
;
; A04 ================================================================
;
mapreg 4,$3a
read data2
mapreg 4,$3d
mapreg 5,$3e
read data3
cdplay audio1,1
jsr dspoff
mapreg 4,$3a
trans $8000,$7000,$2000,MV
_@bg_bank #7,0,0
_@sp_bank #1,0,0,0,0
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work,$20
inc pal_flg
jsr dspon
_@sp_bank #1,0,0,0,0
_@wait 60,_a99
_@sp_bank #2,0,0,0,0
_@wait 60,_a99
_@sp_bank #3,0,0,0,0
_@wait 60,_a99
;
; A05 ================================================================
;
jsr dspoff
memcpy bgpal_work,bgpal_work+$20,$100
memcpy sppal_work,sppal_work+$20,$100
mapreg 4,$3d
mapreg 5,$3e
trans $a000,$1000,$2000,MV
jsr sat_clr
_@pe_bank #4
_@anime_start #$3d,128,0,128,0
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work,$20
inc pal_flg
jsr win_flat
jsr dspon
_@anime_wait _a99
moviw thunder_base,$e0
jsr thunder
cdwait _a99
;
; A06 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
read data6
jsr dspoff
jsr sat_clr
_@bg_bank #6,0,0
_@sp_bank #7,0,-64,0,0
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work,$20
inc pal_flg
jsr win_on
jsr dspon
_@sprscrl_start 0,16,0,1,2
_@wait 7,_a99
moviw thunder_base,$e0
jsr thunder
_scrl_lp_a06:
_@wait 1,_a99
cmpiw2 sprscrl_count,64
bcc _scrl_lp_a06
_@sprscrl_stop
_@wait 60*2,_a99
;
; A07 ================================================================
;
jsr dspoff
memcpy bgpal_work,bgpal_work+$100,$100
memcpy sppal_work,sppal_work+$100,$100
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$1000,$2000*2,MV
jsr sat_clr
_@bg_bank #3,0,0
_@anime_start #$3a,0,0,128,0
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work,$20
inc pal_flg
jsr dspon
_@anime_wait _a99
memcpy pal_bg,bgpal_work+$20,$20
memcpy pal_sp,sppal_work+$20,$20
inc pal_flg
_@wait 30,_a99
memcpy pal_bg,bgpal_work+$40,$20
memcpy pal_sp,sppal_work+$40,$20
inc pal_flg
_@wait 30,_a99
memcpy pal_bg,bgpal_work+$40,$20
memcpy pal_sp,sppal_work+$40,$20
inc pal_flg
_@wait 60,_a99
;
; A08 ================================================================
;
mapreg 4,$3a
mapreg 5,$3b
mapreg 6,$3c
read data8
mapreg 4,$3d
mapreg 5,$3e
mapreg 6,$3f
read data9
read data10
cdplay audio1,2
jsr dspoff
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$1000,$2000*2,MV
trans $0000,$3000,$2000,AV
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work,$20
inc pal_flg
jsr sat_clr
_@bg_bank #4,0,0
_@anime_start #$3a,0,0,128,1
jsr dspon
_@wait 60*2,_a99
_@anime_stop
;
; A09 ================================================================
;
jsr dspoff
memcpy bgpal_work,bgpal_work+$100,$100
memcpy sppal_work,sppal_work+$100,$100
mapreg 5,$3e
mapreg 6,$3f
trans $a000,$1000,$2000*2,MV
jsr sat_clr
_@bg_bank #5,0,0
_@anime_start #$3d,0,0,128,1
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work,$20
inc pal_flg
jsr vsync
jsr dspon
_@wait 60*2,_a99
_@anime_stop
;
; A10 ================================================================
;
jsr dspoff
mapreg 4,$3a
trans $2000,$8000,$2000,AM ;An
trans $4000,$1000,$2000*2,AV ;Sp
trans $c000,$7000,$2000,AV ;Sp
jsr sat_clr
_@bg_bank #6,0,0
_@sp_bank #7,0,48,1,128
_@sp_bank #1,0,0,0,0
_@anime_start #$3a,0,0,0,1
memcpy pal_bg,bgpal_work+$200,$20
memcpy pal_sp,sppal_work+$200,$40
inc pal_flg
jsr vsync
jsr dspon
_@wait 50,_a99
_@sp_bank #7,0,32,1,128
_@wait 50,_a99
_@sp_bank #7,0,16,1,128
_@wait 50,_a99
_@sp_bank #7,0,0,1,128
_@wait 50,_a99
cdwait _a99
;
; A11 ================================================================
;
mapreg 5,$3b
mapreg 6,$3c
read data11
mapreg 5,$3e
read data13
_@anime_stop ;C10 anime
cdplay audio1,3
jsr dspoff
jsr sat_clr
_@bg_bank #3,0,0
_@palc_start pal_bg,bgpal_work,bgpal_work+$20,4
jsr dspon
_@wait 60*4,_a99
_@palc_stop
;
; A12 ================================================================
;
memcpy bgpal_work,bgpal_work+$100,$100
memcpy sppal_work,sppal_work+$100,$100
mapreg 5,$3b
mapreg 6,$3c
trans $a000,$1000,$2000*2,MV
_@sp_bank #4,0,128-32,0,128
_@sp_bank #1,0,0,1,0
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work,$40
inc pal_flg
_@sprscrl_start 16,16,0,-1,4
_sp_anime_lp_a12:
_@sp_bank #1,0,0,1,0
_@wait 10,_a99
_@sp_bank #2,0,0,1,0
_@wait 10,_a99
cmpiw2 sprscrl_count,128-48
jcc _sp_anime_lp_a12
_@sprscrl_stop
_@wait 60,_a99
;
; A13 ================================================================
;
memcpy bgpal_work,bgpal_work+$200,$100
mapreg 5,$3e
trans $a000,$5000,$2000,MV
jsr dspoff
jsr sat_clr
stzw bgy1
_@bg_bank #5,0,0
memcpy pal_bg,bgpal_work,$20
inc pal_flg
jsr dspon
ldx #2
_thunder_lp_a13:
phx
_@wait 60*1,_a99
moviw thunder_base,$e0
jsr thunder
plx
dex
jne _thunder_lp_a13
_@wait 60*1,_a99
;
; A14 ================================================================
;
memcpy bgpal_work,bgpal_work+$300,$200
memcpy sppal_work,sppal_work+$200,$200
jsr dspoff
trans $0000,$1000,$2000*7,AV
jsr dspoff
jsr win_off
_@pe_bank #1,0,0
_@sp_bank #4,0,0,0,0
_@sp_bank #5,128,0,0,64
_@sp_bank #6,0,128,0,64*2
_@sp_bank #7,128,128,0,64*3
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work,$20
inc pal_flg
jsr dspon
_@wait 60,_a99
_@palc_start pal_sp,sppal_work+$20,sppal_work+$60,10
_@wait 10*(3-1),_a99
_@palc_stop
_@wait 10,_a99
memcpy pal_sp,sppal_work+$40,$20
inc pal_flg
_@wait 60,_a99
moviw thunder_base,$140
jsr thunder
memcpy pal_bg,bgpal_work,$20
memcpy pal_sp,sppal_work+$40,$20
inc pal_flg
jsr vsync
cdwait _a99
_@fadeout_start pal_bg,pal_sp,1,14
_@fadeout_wait _a99
;
; A99 ================================================================
;
jsr dspoff
jsr bgpal_clr
jsr sppal_clr
jsr sat_clr
_a99:
jsr all_done
;
; save common area
;
sei
clx
_move_lp:
lda $3f00,x
sta $2000,x
inx
bne _move_lp
;
; call title prog
;
CDEXEC T_BIN,$4000,1
;
thunder_base dw $e0
thunder:
phx
moviw src,bgpal_work
addmw src,thunder_base
ldx #8
_thunder_lp:
phx
moviw dst,pal_bg
phm src
ldy #$20
jsr movsb
plm src
addiw src,2048+$300
moviw dst,pal_sp
phm src
ldy #$20
jsr movsb
plm src
inc pal_flg
_@wait 2,_a99
subiw src,2048+$300+$20
plx
dex
bne _thunder_lp
plx
rts
end